Searched defs:Reg (Results 151 - 175 of 193) sorted by relevance

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/external/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h349 * Reg - All possible values of the reg field in the ModR/M byte.
356 } Reg; typedef in typeref:enum:__anon9805
498 Reg vvvv;
521 Reg opcodeRegister;
529 Reg regBase;
536 Reg reg;
/external/clang/lib/StaticAnalyzer/Core/
H A DExprEngine.cpp199 SVal Reg = loc::MemRegionVal(MRMgr.getCXXTempObjectRegion(Inner, LC)); local
200 State = State->bindLoc(Reg, V);
206 Reg = StoreMgr.evalDerivedToBase(Reg, *I);
209 State = State->BindExpr(Result ? Result : Ex, LC, Reg);
/external/llvm/lib/CodeGen/AsmPrinter/
H A DAsmPrinter.cpp800 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false); local
802 for (MCSuperRegIterator SR(MLoc.getReg(), TRI); SR.isValid() && Reg < 0;
804 Reg = TRI->getDwarfRegNum(*SR, false);
814 // probably assert that Reg >= 0 once debug info generation is more mature.
817 if (Reg < 32) {
819 dwarf::OperationEncodingString(dwarf::DW_OP_breg0 + Reg));
820 EmitInt8(dwarf::DW_OP_breg0 + Reg);
824 OutStreamer.AddComment(Twine(Reg));
825 EmitULEB128(Reg);
829 if (Reg < 3
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H A DDwarfCompileUnit.cpp354 void CompileUnit::addRegisterOp(DIE *TheDie, unsigned Reg) { argument
356 unsigned DWReg = RI->getDwarfRegNum(Reg, false);
366 void CompileUnit::addRegisterOffset(DIE *TheDie, unsigned Reg, argument
369 unsigned DWReg = RI->getDwarfRegNum(Reg, false);
371 if (Reg == TRI->getFrameRegister(*Asm->MF))
H A DDwarfDebug.cpp1463 unsigned Reg = *AI; local
1464 const MDNode *Var = LiveUserVar[Reg];
1467 // Reg is now clobbered.
1468 LiveUserVar[Reg] = 0;
1470 // Was MD last defined by a DBG_VALUE referring to Reg?
1482 // Is the variable still in Reg?
1484 Prev->getOperand(0).getReg() != Reg)
/external/llvm/lib/CodeGen/
H A DIfConversion.cpp972 unsigned Reg = *I; local
973 Redefs.insert(Reg);
974 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
987 unsigned Reg = MO.getReg(); local
988 if (!Reg)
991 Defs.push_back(Reg);
993 Redefs.erase(Reg);
994 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
1000 unsigned Reg = Defs[i]; local
1001 if (!Redefs.insert(Reg)) {
1336 unsigned Reg = MO.getReg(); local
1351 unsigned Reg = Defs[i]; local
1424 unsigned Reg = MO.getReg(); local
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H A DMachineInstr.cpp49 void MachineOperand::setReg(unsigned Reg) { argument
50 if (getReg() == Reg) return; // No change.
60 SmallContents.RegNo = Reg;
66 SmallContents.RegNo = Reg;
69 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, argument
71 assert(TargetRegisterInfo::isVirtualRegister(Reg));
74 setReg(Reg);
79 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { argument
80 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
82 Reg
129 ChangeToRegister(unsigned Reg, bool isDef, bool isImp, bool isKill, bool isDead, bool isUndef, bool isDebug) argument
997 findRegisterUseOperandIdx(unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const argument
1021 readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl<unsigned> *Ops) const argument
1050 findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, const TargetRegisterInfo *TRI) const argument
1359 unsigned Reg = getOperand(1).getReg(); local
1455 unsigned Reg = getOperand(StartOp).getReg(); local
1515 unsigned Reg = MO.getReg(); local
1668 unsigned Reg = MO.getReg(); local
1715 clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo) argument
1741 unsigned Reg = MO.getReg(); local
1810 unsigned Reg = MO.getReg(); local
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H A DRegisterCoalescer.cpp821 unsigned Reg = NewMIImplDefs[i]; local
822 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
1384 unsigned Reg = MI->getOperand(1).getReg(); local
1385 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1387 LiveRangeQuery LRQ(LIS->getInterval(Reg), VNI->def);
1709 /// Return true if MI uses any of the given Lanes from Reg.
1710 /// This does not include partial redefinitions of Reg.
1711 bool JoinVals::usesLanes(MachineInstr *MI, unsigned Reg, unsigned SubIdx, argument
1716 if (!MO->isReg() || MO->isDef() || MO->getReg() != Reg)
1890 unsigned Reg local
2174 unsigned Reg = InflateRegs[i]; local
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp1 //===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===//
235 void releaseInterferences(unsigned Reg = 0);
289 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); local
290 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
1135 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, argument
1171 SDep FromDep(SU, SDep::Data, Reg);
1190 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, argument
1196 if (Reg == *ImpDef)
1205 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg, argument
1210 for (MCRegAliasIterator AliasI(Reg, TR
1289 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); local
1328 releaseInterferences(unsigned Reg) argument
1395 unsigned Reg = LRegs[j]; local
1438 unsigned Reg = LRegs[0]; local
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H A DSelectionDAGISel.cpp400 unsigned Reg = MI->getOperand(0).getReg(); local
401 if (TargetRegisterInfo::isPhysicalRegister(Reg))
404 MachineInstr *Def = RegInfo->getVRegDef(Reg);
410 // If Reg is live-in then update debug info to track its copy in a vreg.
411 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
822 unsigned Reg = TLI.getExceptionPointerRegister(); local
823 if (Reg) MBB->addLiveIn(Reg);
826 Reg = TLI.getExceptionSelectorRegister();
827 if (Reg) MB
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/external/llvm/lib/MC/
H A DMCDwarf.cpp877 unsigned Reg = Loc.getReg() == MachineLocation::VirtualFP ? local
881 MachineLocation(Reg) : MachineLocation(Reg, Loc.getOffset());
988 unsigned Reg = Instr.getRegister(); local
991 Streamer.AddComment(Twine("Reg ") + Twine(Reg));
994 Streamer.EmitULEB128IntValue(Reg);
1023 Streamer.AddComment(Twine("Reg ") + Twine(Instr.getRegister()));
1041 Streamer.AddComment(Twine("Reg ") + Twine(Instr.getRegister()));
1052 unsigned Reg local
1090 unsigned Reg = Instr.getRegister(); local
1098 unsigned Reg = Instr.getRegister(); local
1339 unsigned Reg = Src.getReg(); local
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/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp206 struct RegOp Reg; member in union:__anon9643::AArch64Operand::__anon9644
232 return Reg.RegNum;
741 Op->Reg.RegNum = RegNum;
747 Op->Reg.RegNum = RegNum;
/external/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp235 unsigned Reg = MLoc.getReg(); local
236 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
242 unsigned SReg = Reg - ARM::S0;
263 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
269 unsigned QReg = Reg - ARM::Q0;
342 unsigned Reg = MO.getReg(); local
343 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
345 if(ARM::GPRPairRegClass.contains(Reg)) {
446 unsigned Reg = MI->getOperand(OpNum).getReg(); local
512 unsigned Reg = MO.getReg(); local
521 unsigned Reg = MI->getOperand(OpNum).getReg(); local
540 unsigned Reg = MO.getReg(); local
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H A DARMCodeEmitter.cpp267 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg()); local
273 Binary |= (Reg << 13);
322 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg()); local
H A DARMConstantIslandPass.cpp1813 unsigned Reg = CmpMI->getOperand(0).getReg(); local
1817 isARMLowRegister(Reg)) {
1822 .addReg(Reg).addMBB(DestBB,Br.MI->getOperand(0).getTargetFlags());
H A DARMLoadStoreOptimizer.cpp81 unsigned Reg; member in struct:__anon9669::ARMLoadStoreOpt::MemOpQueueEntry
88 : Offset(o), Reg(r), isKill(k), Position(p), MBBI(i), Merged(false) {}
387 unsigned Reg = memOps[i].Reg; local
388 KilledRegs.insert(Reg);
389 Killer[Reg] = i;
396 unsigned Reg = memOps[i].Reg; local
399 bool isKill = memOps[i].isKill || KilledRegs.count(Reg);
400 Regs.push_back(std::make_pair(Reg, isKil
424 unsigned Reg = Regs[i-memOpsBegin].first; local
484 unsigned Reg = MO.getReg(); local
1072 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument
1245 unsigned Reg = MO.getReg(); local
1526 unsigned Reg = MO.getReg(); local
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/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMBaseInfo.h166 static inline bool isARMLowRegister(unsigned Reg) { argument
168 switch (Reg) {
/external/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp120 /// If successful, it will return true and set the \p Reg, \p IVBump
130 bool findInductionRegister(MachineLoop *L, unsigned &Reg,
236 unsigned Reg; member in struct:__anon9699::CountValue::Values::__anon9700
246 Contents.R.Reg = v;
257 return Contents.R.Reg;
270 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
320 unsigned &Reg,
416 Reg = F->second.first;
906 unsigned Reg = MO.getReg(); local
907 if (MRI->use_nodbg_empty(Reg))
319 findInductionRegister(MachineLoop *L, unsigned &Reg, int64_t &IVBump, MachineInstr *&IVOp ) const argument
960 unsigned Reg = MO.getReg(); local
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H A DHexagonISelLowering.cpp177 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
178 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
191 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
192 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
202 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) {
203 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
248 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
249 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
263 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
264 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocV
705 unsigned Reg = local
983 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); local
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/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp34 bool setATReg(unsigned Reg);
235 struct RegOp Reg; member in union:__anon9734::MipsOperand::__anon9735
285 return Reg.RegNum;
290 Reg.Kind = RegKind;
319 Op->Reg.RegNum = RegNum;
344 return Kind == k_Register && Reg.Kind == Kind_CPURegs;
347 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
351 return Kind == k_Register && Reg.Kind == Kind_CPU64Regs;
354 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
359 return Reg
705 setATReg(unsigned Reg) argument
1355 const AsmToken &Reg = Parser.getTok(); local
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/external/llvm/lib/Target/X86/
H A DX86FastISel.cpp507 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
516 // FIXME: How do we know Base.Reg is free??
517 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
526 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
527 AM.Base.Reg = X86::RIP;
544 StubAM.Base.Reg = AM.Base.Reg;
556 StubAM.Base.Reg = X86::RIP;
576 AM.Base.Reg = LoadReg;
584 if (AM.Base.Reg
756 unsigned Reg = getRegForValue(RV); local
821 unsigned Reg = X86MFInfo->getSRetReturnReg(); local
1385 unsigned Reg; local
2101 unsigned Reg = getRegForValue(I->getOperand(0)); local
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/external/llvm/utils/TableGen/
H A DAsmMatcherEmitter.cpp381 static ResOperand getRegOp(Record *Reg) { argument
384 X.Register = Reg;
778 if (Record *Reg = AsmOperands[i].SingletonReg)
779 SingletonRegisters.insert(Reg);
934 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
935 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
943 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
944 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
1110 CI->ClassName = "Reg" + utostr(Index);
1656 Record *Reg local
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H A DCodeGenRegisters.cpp136 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]); local
137 ExplicitAliases.push_back(Reg);
138 Reg->ExplicitAliases.push_back(this);
624 Record *Reg = Lists[i][n]; local
626 Name += Reg->getName();
627 Tuple.push_back(DefInit::get(Reg));
629 unsigned(Reg->getValueAsInt("CostPerUse")));
729 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]); local
730 Members.insert(Reg);
731 TopoSigs.set(Reg
741 CodeGenRegister *Reg = RegBank.getReg(Order.back()); local
1066 CodeGenRegister *&Reg = Def2Reg[Def]; local
1303 const CodeGenRegister *Reg = Registers[i]; local
1324 const CodeGenRegister *Reg = 0; local
1366 normalizeWeight(CodeGenRegister *Reg, std::vector<UberRegSet> &UberSets, std::vector<UberRegSet*> &RegSets, std::set<unsigned> &NormalRegs, CodeGenRegister::RegUnitList &NormalUnits, CodeGenRegBank &RegBank) argument
1834 const CodeGenRegister *Reg = getReg(R); local
1879 CodeGenRegister *Reg = getReg(Regs[i]); local
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H A DDAGISelMatcher.h818 /// Reg - The def for the register that we're emitting. If this is null, then
820 const CodeGenRegister *Reg; member in class:llvm::EmitRegisterMatcher
824 : Matcher(EmitRegister), Reg(reg), VT(vt) {}
826 const CodeGenRegister *getReg() const { return Reg; }
836 return cast<EmitRegisterMatcher>(M)->Reg == Reg &&
840 return ((unsigned)(intptr_t)Reg) << 4 | VT;
/external/qemu/target-i386/
H A Dops_sse.h22 #define Reg MMXReg macro
30 #define Reg XMMReg macro
39 void glue(helper_psrlw, SUFFIX)(Reg *d, Reg *s)
63 void glue(helper_psraw, SUFFIX)(Reg *d, Reg *s)
84 void glue(helper_psllw, SUFFIX)(Reg *d, Reg *s)
108 void glue(helper_psrld, SUFFIX)(Reg *d, Reg *
2027 #undef Reg macro
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