| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL enumerator in enum:llvm::MSP430ISD::__anon9729
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 91 SRL, SRA, SHL, enumerator in enum:llvm::PPCISD::NodeType
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 318 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
382 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
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| /external/llvm/include/llvm/TableGen/ |
| H A D | Record.h | 930 enum BinaryOp { ADD, SHL, SRA, SRL, STRCONCAT, CONCAT, EQ }; enumerator in enum:llvm::BinOpInit::BinaryOp
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 880 if (Opc == ISD::SRA)
1122 case ISD::SRA: return visitSRA(N);
1205 case ISD::SRA:
1895 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1907 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, local
1913 return SRA;
1915 AddToWorkList(SRA.getNode());
1917 DAG.getConstant(0, VT), SRA);
2096 return DAG.getNode(ISD::SRA,
3815 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, local
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 796 setOperationAction(ISD::SRA, VT, Expand);
1053 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1054 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1063 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1071 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1136 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1137 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1195 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1220 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1326 setTargetDAGCombine(ISD::SRA);
11480 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG); local
[all...] |