/external/llvm/utils/TableGen/ |
H A D | CallingConvEmitter.cpp | 88 Record *VT = VTs->getElementAsRecord(i); local 90 O << "LocVT == " << getEnumName(getValueType(VT));
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H A D | DAGISelMatcher.cpp | 210 OS.indent(indent) << "EmitInteger " << Val << " VT=" << VT << '\n'; local 215 OS.indent(indent) << "EmitStringInteger " << Val << " VT=" << VT << '\n'; local 224 OS << " VT=" << VT << '\n'; local 293 return HashString(Val) ^ VT;
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H A D | CodeGenTarget.cpp | 468 MVT::SimpleValueType VT; local 473 VT = OverloadedVTs[MatchTy]; 479 VT == MVT::iAny || VT == MVT::vAny) && 482 VT = getValueType(TyEl->getValueAsDef("VT")); 484 if (EVT(VT).isOverloaded()) { 485 OverloadedVTs.push_back(VT); 490 if (VT == MVT::isVoid) 493 IS.RetVTs.push_back(VT); 502 MVT::SimpleValueType VT; local [all...] |
/external/clang/include/clang/AST/ |
H A D | DeclContextInternals.h | 171 DeclsTy *VT = new DeclsTy(); local 172 VT->push_back(OldD); 173 Data = VT;
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/external/llvm/lib/CodeGen/ |
H A D | CallingConvLower.cpp | 72 MVT ArgVT = Ins[i].VT; 90 MVT VT = Outs[i].VT; local 92 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) 104 MVT VT = Outs[i].VT; local 106 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) { 109 << EVT(VT) 158 MVT VT = Ins[i].VT; local 172 AnalyzeCallResult(MVT VT, CCAssignFn Fn) argument [all...] |
H A D | TargetLoweringBase.cpp | 631 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 635 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 636 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 640 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 641 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 759 /// VT must be a legal type. 760 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 761 assert(isTypeLegal(VT)); 776 getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI) argument 952 MVT VT = (MVT::SimpleValueType)i; local 1051 getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const argument 1129 EVT VT = ValueVTs[j]; local [all...] |
/external/llvm/lib/IR/ |
H A D | ValueTypes.cpp | 29 EVT VT; local 30 VT.LLVMTy = IntegerType::get(Context, BitWidth); 31 assert(VT.isExtended() && "Type is not extended!"); 32 return VT; 35 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT, argument 38 ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(Context), NumElements);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.cpp | 52 EVT VT = MVT::i32; local 66 Loads[i] = DAG.getLoad(VT, dl, Chain, 98 VT = MVT::i16; 101 VT = MVT::i8; 105 Loads[i] = DAG.getLoad(VT, dl, Chain, 121 VT = MVT::i16; 124 VT = MVT::i8;
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCallingConvLower.cpp | 81 EVT ArgVT = Ins[i].VT; 117 EVT VT = Outs[i].VT; local 119 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this, -1, -1, false)){ 121 << VT.getEVTString() << "\n"; 147 EVT ArgVT = Outs[i].VT; 185 EVT VT = Ins[i].VT; local 187 if (Fn(i, VT, V 197 AnalyzeCallResult(EVT VT, Hexagon_CCAssignFn Fn) argument [all...] |
/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeISelDAGToDAG.cpp | 211 EVT VT = Node->getValueType(0); local 212 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT); 215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm); 216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 78 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { argument 79 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
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H A D | Mips16ISelDAGToDAG.cpp | 267 EVT VT = LHS.getValueType(); local 270 SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops, 2); 272 SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT, 275 SDNode *Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
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H A D | MipsSEISelDAGToDAG.cpp | 212 EVT VT = LHS.getValueType(); local 214 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops, 2); 215 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT, 217 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
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/external/llvm/lib/Target/X86/Utils/ |
H A D | X86ShuffleDecode.cpp | 64 void DecodePALIGNRMask(MVT VT, unsigned Imm, argument 66 unsigned NumElts = VT.getVectorNumElements(); 67 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8); 69 unsigned NumLanes = VT.getSizeInBits() / 128; 83 /// VT indicates the type of the vector allowing it to handle different 85 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument 86 unsigned NumElts = VT.getVectorNumElements(); 88 unsigned NumLanes = VT.getSizeInBits() / 128; 101 void DecodePSHUFHWMask(MVT VT, unsigned Imm, argument 103 unsigned NumElts = VT 117 DecodePSHUFLWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 136 DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 158 DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) argument 178 DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) argument 195 DecodeVPERM2X128Mask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument [all...] |
/external/clang/lib/CodeGen/ |
H A D | CodeGenTypes.cpp | 459 const VectorType *VT = cast<VectorType>(Ty); local 460 ResultType = llvm::VectorType::get(ConvertType(VT->getElementType()), 461 VT->getNumElements());
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/external/guava/guava/src/com/google/common/base/ |
H A D | Ascii.java | 167 public static final byte VT = 11; field in class:Ascii
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/external/llvm/include/llvm/Target/ |
H A D | TargetCallingConv.h | 113 MVT VT; member in struct:llvm::ISD::InputArg 124 InputArg() : VT(MVT::Other), Used(false) {} 128 VT = vt.getSimpleVT(); 138 MVT VT; member in struct:llvm::ISD::OutputArg 156 VT = vt.getSimpleVT();
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FunctionLoweringInfo.cpp | 172 EVT VT = ValueVTs[vti]; local 173 unsigned NumRegisters = TLI.getNumRegisters(Fn->getContext(), VT); 210 unsigned FunctionLoweringInfo::CreateReg(MVT VT) { argument 211 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); 272 "PHIs with non-vector integer types should have a single VT.");
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H A D | InstrEmitter.cpp | 102 MVT VT = Node->getSimpleValueType(ResNo); local 105 if (TLI->isTypeLegal(VT)) 106 UseRC = TLI->getRegClassFor(VT); 127 MVT VT = Node->getSimpleValueType(Op.getResNo()); local 128 if (VT == MVT::Other || VT == MVT::Glue) 157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 163 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 166 DstRC = TLI->getRegClassFor(VT); 425 MVT VT, DebugLo [all...] |
H A D | SelectionDAGPrinter.cpp | 93 EVT VT = Op.getValueType(); local 94 if (VT == MVT::Glue) 96 else if (VT == MVT::Other)
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H A D | ResourcePriorityQueue.cpp | 97 MVT VT = ScegN->getSimpleValueType(i); local 98 if (TLI->isTypeLegal(VT) 99 && (TLI->getRegClassFor(VT)->getID() == RCId)) { 135 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); local 136 if (TLI->isTypeLegal(VT) 137 && (TLI->getRegClassFor(VT)->getID() == RCId)) { 335 MVT VT = SU->getNode()->getSimpleValueType(i); local 336 if (TLI->isTypeLegal(VT) 337 && TLI->getRegClassFor(VT) 338 && TLI->getRegClassFor(VT) 344 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); local 488 MVT VT = ScegN->getSimpleValueType(i); local 499 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86AsmPrinter.cpp | 245 MVT::SimpleValueType VT = (strcmp(Modifier+6,"64") == 0) ? local 248 Reg = getX86SubSuperRegister(Reg, VT);
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H A D | X86RegisterInfo.cpp | 519 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT, argument 521 switch (VT) { 522 default: llvm_unreachable("Unexpected VT");
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 116 EVT VT = Op.getValueType(); local 123 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); 127 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1)); 129 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1), 132 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1), 135 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1), 138 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1), 141 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1), 144 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1), 147 return DAG.getNode(ISD::FRINT, DL, VT, O 156 EVT VT = Op.getValueType(); local 168 EVT VT = Op.getValueType(); local 183 EVT VT = Op.getValueType(); local 244 EVT VT = Op.getValueType(); local [all...] |
H A D | AMDILISelLowering.cpp | 96 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x]; local 100 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); 101 setOperationAction(ISD::SUBE, VT, Expand); 102 setOperationAction(ISD::SUBC, VT, Expand); 103 setOperationAction(ISD::ADDE, VT, Expand); 104 setOperationAction(ISD::ADDC, VT, Expand); 105 setOperationAction(ISD::BRCOND, VT, Custom); 106 setOperationAction(ISD::BR_JT, VT, Expand); 107 setOperationAction(ISD::BRIND, VT, Expand); 109 setOperationAction(ISD::SREM, VT, Expan 117 MVT::SimpleValueType VT = (MVT::SimpleValueType)FloatTypes[x]; local 132 MVT::SimpleValueType VT = (MVT::SimpleValueType)IntTypes[x]; local 152 MVT::SimpleValueType VT = (MVT::SimpleValueType)VectorTypes[ii]; local [all...] |