/external/eigen/test/ |
H A D | product_trsolve.cpp | 12 #define VERIFY_TRSM(TRI,XB) { \ 14 (TRI).solveInPlace(XB); \ 15 VERIFY_IS_APPROX((TRI).toDenseMatrix() * (XB), ref); \ 17 (XB) = (TRI).solve(XB); \ 18 VERIFY_IS_APPROX((TRI).toDenseMatrix() * (XB), ref); \ 21 #define VERIFY_TRSM_ONTHERIGHT(TRI,XB) { \ 23 (TRI).transpose().template solveInPlace<OnTheRight>(XB.transpose()); \ 24 VERIFY_IS_APPROX((XB).transpose() * (TRI).transpose().toDenseMatrix(), ref.transpose()); \ 26 (XB).transpose() = (TRI).transpose().template solve<OnTheRight>(XB.transpose()); \ 27 VERIFY_IS_APPROX((XB).transpose() * (TRI) [all...] |
H A D | product_mmtr.cpp | 12 #define CHECK_MMTR(DEST, TRI, OP) { \ 14 DEST.template triangularView<TRI>() OP; \ 16 ref2.template triangularView<TRI>() = ref1; \
|
/external/llvm/lib/CodeGen/ |
H A D | CriticalAntiDepBreaker.cpp | 34 TRI(MF.getTarget().getRegisterInfo()), 36 Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)), 37 KillIndices(TRI->getNumRegs(), 0), 38 DefIndices(TRI->getNumRegs(), 0), 39 KeepRegs(TRI->getNumRegs(), false) {} 46 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { 65 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { 78 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { 80 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { 100 for (unsigned Reg = 0; Reg != TRI [all...] |
H A D | RegAllocFast.cpp | 58 const TargetRegisterInfo *TRI; member in class:__anon9501::RAFast 125 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) 131 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) 240 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true); 285 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI) 286 << " in " << PrintReg(LR.PhysReg, TRI)); 290 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI); 368 for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) { 374 assert(TRI->isSuperRegister(PhysReg, Alias) && 378 MO.getParent()->addRegisterKilled(Alias, TRI, tru [all...] |
H A D | InterferenceCache.cpp | 32 TRI = tri; 33 PhysRegEntries.assign(TRI->getNumRegs(), 0); 41 if (!Entries[E].valid(LIUArray, TRI)) 42 Entries[E].revalidate(LIUArray, TRI); 56 Entries[E].reset(PhysReg, LIUArray, TRI, MF); 65 const TargetRegisterInfo *TRI) { 71 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) 77 const TargetRegisterInfo *TRI, 88 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 95 const TargetRegisterInfo *TRI) { 64 revalidate(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI) argument 75 reset(unsigned physReg, LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI, const MachineFunction *MF) argument 94 valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI) argument [all...] |
H A D | LocalStackSlotAllocation.cpp | 86 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local 91 if (!TRI->requiresVirtualBaseRegisters(MF) || LocalObjectCount == 0) 202 const TargetRegisterInfo *TRI) { 209 if (TRI->isFrameOffsetLegal(MI, Offset)) 225 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); local 289 if (TRI->needsFrameBaseReg(MI, LocalOffsets[FrameIdx])) { 306 MI, TRI)) { 316 int64_t InstrOffset = TRI->getFrameIndexInstrOffset(MI, idx); 318 const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF); 328 TRI 197 lookupCandidateBaseReg(const SmallVector<std::pair<unsigned, int64_t>, 8> &Regs, std::pair<unsigned, int64_t> &RegOffset, int64_t FrameSizeAdjust, int64_t LocalFrameOffset, const MachineInstr *MI, const TargetRegisterInfo *TRI) argument [all...] |
H A D | VirtRegMap.cpp | 55 TRI = mf.getTarget().getRegisterInfo(); 121 OS << '[' << PrintReg(Reg, TRI) << " -> " 122 << PrintReg(Virt2PhysMap[Reg], TRI) << "] " 130 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] 156 const TargetRegisterInfo *TRI; member in class:__anon9547::VirtRegRewriter 204 TRI = TM->getRegisterInfo(); 315 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg()); 327 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true); 330 MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true); 333 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI); [all...] |
H A D | LiveStackAnalysis.cpp | 51 TRI = MF.getTarget().getRegisterInfo(); 68 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
|
H A D | LiveVariables.cpp | 197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { 219 if (TRI->isSubRegister(Reg, DefReg)) { 221 for (MCSubRegIterator SubRegs(DefReg, TRI); SubRegs.isValid(); ++SubRegs) 251 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { 263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) 275 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 290 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { 339 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { 354 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) 369 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, tru [all...] |
H A D | DeadMachineInstructionElim.cpp | 32 const TargetRegisterInfo *TRI; member in class:__anon9451::DeadMachineInstructionElim 89 TRI = MF.getTarget().getRegisterInfo(); 161 for (MCSubRegIterator SR(Reg, TRI); SR.isValid(); ++SR) 176 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
|
H A D | RegisterCoalescer.cpp | 82 const TargetRegisterInfo* TRI; member in class:__anon9508::RegisterCoalescer 258 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub)) 276 Dst = TRI.getSubReg(Dst, DstSub); 283 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src)); 300 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, 307 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); 311 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); 314 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); 353 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub)) 371 Dst = TRI 1233 const TargetRegisterInfo *TRI; member in class:__anon9509::JoinVals [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterPressure.h | 43 void increase(unsigned Reg, const TargetRegisterInfo *TRI, 50 void decrease(unsigned Reg, const TargetRegisterInfo *TRI, 53 void dump(const TargetRegisterInfo *TRI) const; 171 const TargetRegisterInfo *TRI; member in class:llvm::RegPressureTracker 199 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(true) {} 202 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(false) {}
|
H A D | MachineInstr.h | 717 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { 718 return findRegisterUseOperandIdx(Reg, false, TRI) != -1; 738 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { 739 return findRegisterUseOperandIdx(Reg, true, TRI) != -1; 746 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const { 747 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1; 753 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const { 754 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1; 761 const TargetRegisterInfo *TRI = NULL) const { 762 return findRegisterDefOperandIdx(Reg, true, false, TRI) ! [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 20 const TargetRegisterInfo &TRI) { 30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); 61 hasRAWHazard(DefMI, MI, TRI))) { 19 hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, const TargetRegisterInfo &TRI) argument
|
H A D | ARMFrameLowering.h | 42 const TargetRegisterInfo *TRI) const; 47 const TargetRegisterInfo *TRI) const;
|
H A D | Thumb2ITBlockPass.cpp | 32 const TargetRegisterInfo *TRI; member in class:__anon9693::Thumb2ITBlockPass 57 const TargetRegisterInfo *TRI) { 77 for (MCSubRegIterator Subreg(Reg, TRI); Subreg.isValid(); ++Subreg) 84 for (MCSubRegIterator Subreg(Reg, TRI); Subreg.isValid(); ++Subreg) 178 TrackDefUses(MI, Defs, Uses, TRI); 224 TrackDefUses(NMI, Defs, Uses, TRI); 252 TRI = TM.getRegisterInfo(); 54 TrackDefUses(MachineInstr *MI, SmallSet<unsigned, 4> &Defs, SmallSet<unsigned, 4> &Uses, const TargetRegisterInfo *TRI) argument
|
H A D | ARMBaseInstrInfo.cpp | 718 const TargetRegisterInfo *TRI = &getRegisterInfo(); local 722 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { 730 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing); 731 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing); 745 Mov->addRegisterDefined(DestReg, TRI); 747 Mov->addRegisterKilled(SrcReg, TRI); 753 const TargetRegisterInfo *TRI) { 758 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 766 const TargetRegisterInfo *TRI) cons 751 AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) argument 1138 const TargetRegisterInfo *TRI = &getRegisterInfo(); local 2114 const TargetRegisterInfo *TRI = &getRegisterInfo(); local 3039 getBundledDefMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist) argument 3063 getBundledUseMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist) argument 3762 getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, unsigned SReg, unsigned &Lane) argument 3792 getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, MachineInstr *MI, unsigned DReg, unsigned Lane, unsigned &ImplicitSReg) argument 3825 const TargetRegisterInfo *TRI = &getRegisterInfo(); local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsSEFrameLowering.h | 38 const TargetRegisterInfo *TRI) const;
|
H A D | MipsSEInstrInfo.h | 56 const TargetRegisterInfo *TRI) const; 62 const TargetRegisterInfo *TRI) const;
|
H A D | Mips16InstrInfo.h | 55 const TargetRegisterInfo *TRI) const; 61 const TargetRegisterInfo *TRI) const;
|
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.h | 64 const TargetRegisterInfo *TRI) const; 69 const TargetRegisterInfo *TRI) const;
|
/external/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.h | 94 const TargetRegisterInfo *TRI) const; 100 const TargetRegisterInfo *TRI) const;
|
/external/llvm/lib/Target/X86/ |
H A D | X86FrameLowering.h | 54 const TargetRegisterInfo *TRI) const; 59 const TargetRegisterInfo *TRI) const;
|
/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.h | 73 const TargetRegisterInfo *TRI) const; 79 const TargetRegisterInfo *TRI) const;
|
/external/llvm/include/llvm/Target/ |
H A D | TargetFrameLowering.h | 134 const TargetRegisterInfo *TRI) const { 145 const TargetRegisterInfo *TRI) const {
|