Searched refs:FSUB (Results 1 - 25 of 33) sorted by relevance

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/external/javassist/src/main/javassist/bytecode/
H A DOpcode.java110 int FSUB = 102; field in interface:Opcode
/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h234 FADD, FSUB, FMUL, FMA, FDIV, FREM, enumerator in enum:llvm::ISD::NodeType
/external/qemu/target-i386/
H A Dops_sse_header.h69 SSE_HELPER_B(psubb, FSUB)
70 SSE_HELPER_W(psubw, FSUB)
71 SSE_HELPER_L(psubl, FSUB)
72 SSE_HELPER_Q(psubq, FSUB)
H A Dops_sse.h334 #define FSUB(a, b) ((a) - (b)) macro
367 SSE_HELPER_B(helper_psubb, FSUB)
368 SSE_HELPER_W(helper_psubw, FSUB)
369 SSE_HELPER_L(helper_psubl, FSUB)
370 SSE_HELPER_Q(helper_psubq, FSUB)
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp59 // Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB
201 case ISD::FSUB:
735 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
737 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
H A DSelectionDAGBuilder.cpp2643 visitBinary(I, ISD::FSUB);
3718 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3834 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3851 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3857 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3876 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3882 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3888 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3928 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3945 SDValue t3 = DAG.getNode(ISD::FSUB, d
[all...]
H A DSelectionDAGDumper.cpp178 case ISD::FSUB: return "fsub";
H A DLegalizeFloatTypes.cpp93 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break;
822 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break;
1365 DAG.getNode(ISD::FSUB, dl,
H A DSelectionDAG.cpp2648 if (getTarget().Options.UnsafeFPMath && OpOpcode == ISD::FSUB)
2649 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1),
2857 case ISD::FSUB:
2871 } else if (Opcode == ISD::FSUB) {
3118 case ISD::FSUB:
3165 case ISD::FSUB:
3204 case ISD::FSUB:
H A DDAGCombiner.cpp422 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
432 case ISD::FSUB:
485 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
490 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
494 case ISD::FSUB:
504 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
1140 case ISD::FSUB: return visitFSUB(N);
5820 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5822 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5825 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, V
[all...]
H A DLegalizeVectorTypes.cpp104 case ISD::FSUB:
557 case ISD::FSUB:
1386 case ISD::FSUB:
H A DLegalizeDAG.cpp2265 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2303 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2922 DAG.getNode(ISD::FSUB, dl, VT,
3126 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3283 case ISD::FSUB: {
H A DFastISel.cpp980 return SelectBinaryOp(I, ISD::FSUB);
/external/valgrind/main/none/tests/ppc32/
H A Dround.c32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator in enum:__anon15351
929 case FSUB:
1084 case FSUB:
/external/valgrind/main/none/tests/ppc64/
H A Dround.c32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator in enum:__anon15394
929 case FSUB:
1084 case FSUB:
/external/javassist/src/main/javassist/compiler/
H A DCodeGen.java935 '-', DSUB, FSUB, LSUB, ISUB,
1730 bytecode.addOpcode(token == PLUSPLUS ? FADD : FSUB);
1808 bytecode.addOpcode(token == PLUSPLUS ? FADD : FSUB);
/external/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp169 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
H A DR600ISelLowering.cpp41 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
56 setOperationAction(ISD::FSUB, MVT::f32, Expand);
H A DAMDILISelLowering.cpp178 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
/external/javassist/src/main/javassist/bytecode/analysis/
H A DExecutor.java324 case FSUB:
/external/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1194 case FSub: return ISD::FSUB;
/external/dexmaker/lib/
H A Djarjar.jarMETA-INF/ META-INF/MANIFEST.MF com/ com/tonicsystems/ com/tonicsystems/jarjar/ com/tonicsystems/jarjar/AbstractDepHandler ...
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp224 setOperationAction(ISD::FSUB, MVT::f128, Custom);
2317 case ISD::FSUB: return LowerF128ToCall(Op, DAG, RTLIB::SUB_F128);
/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1834 case ISD::FSUB:
2765 return SelectBinaryFPOp(I, ISD::FSUB);
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4615 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4621 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4627 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4633 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);

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