Searched refs:Op4 (Results 1 - 5 of 5) sorted by relevance

/external/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp643 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local
648 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
652 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
677 unsigned Op1, Op2, Op3, Op4, Op5; local
682 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
687 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
698 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); local
703 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
706 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
717 unsigned Op4 local
[all...]
/external/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h759 SDValue Op3, SDValue Op4);
761 SDValue Op3, SDValue Op4, SDValue Op5);
/external/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2701 SDValue Op0, Op1, Op2, Op3, Op4; local
2707 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4))
2716 OutOps.push_back(Op4);
H A DX86ISelLowering.cpp11868 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); local
11871 if (!Op1 && !Op2 && !Op3 && Op4)
11875 if (Op1 && !Op2 && !Op3 && !Op4)
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp4968 SDValue Op3, SDValue Op4) {
4969 SDValue Ops[] = { Op1, Op2, Op3, Op4 };
4975 SDValue Op3, SDValue Op4, SDValue Op5) {
4976 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
4967 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4) argument
4974 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) argument

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