Searched refs:RSP (Results 1 - 16 of 16) sorted by relevance

/external/llvm/test/MC/X86/
H A Dintel-syntax-2.s6 mov DWORD PTR [RSP - 4], 257
H A Dintel-syntax.s9 mov DWORD PTR [RSP - 4], 257
11 mov DWORD PTR [RSP + 4], 258
13 mov QWORD PTR [RSP - 16], 123
15 mov BYTE PTR [RSP - 17], 97
17 mov EAX, DWORD PTR [RSP - 4]
19 mov RAX, QWORD PTR [RSP]
21 mov DWORD PTR [RSP - 4], -4
25 mov EAX, DWORD PTR [RSP + 4*RAX - 24]
H A Dintel-syntax-encoding.s25 mov QWORD PTR [RSP - 16], RAX
/external/kernel-headers/original/asm-x86/
H A Dptrace-abi.h50 #define RSP 152 macro
/external/llvm/lib/Target/X86/
H A DX86CompilationCallback_Win64.asm20 ; Save RSP.
53 ; Restore RSP.
H A DX86RegisterInfo.cpp75 StackPtr = X86::RSP;
309 Reserved.set(X86::RSP);
310 for (MCSubRegIterator I(X86::RSP, this); I.isValid(); ++I)
533 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
561 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
598 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
634 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
670 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
671 return X86::RSP;
H A DX86FrameLowering.cpp562 // %RSP<def> = SUB64ri8 %RSP, 48
1495 ScratchReg = X86::RSP;
1497 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1712 SPReg = X86::RSP;
H A DX86CodeEmitter.cpp516 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
554 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
H A DX86ISelLowering.cpp14011 // Allocate by subtracting from RSP
14035 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
14129 // Updates RSP.
14133 .addReg(X86::RSP, RegState::Implicit)
14135 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
14145 // RAX has the offset to subtracted from RSP.
14146 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
14147 .addReg(X86::RSP)
18343 case X86::SP: DestReg = X86::RSP; break;
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp294 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
298 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
H A DX86MCCodeEmitter.cpp344 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
383 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
/external/valgrind/main/VEX/auxprogs/
H A Dgenoffsets.c106 GENOFFSET(AMD64,amd64,RSP);
/external/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h183 ENTRY(RSP) \
/external/valgrind/main/coregrind/m_sigframe/
H A Dsigframe-amd64-linux.c360 SC2(rsp,RSP);
515 /* tst->m_rsp = rsp; also notify the tool we've updated RSP */
528 VG_(printf)("pushed signal frame; %%RSP now = %#lx, "
/external/strace/
H A Dprocess.c2693 { 8*RSP, "8*RSP" },
/external/valgrind/main/memcheck/
H A Dmc_machine.c569 if (o == GOF(RSP) && is1248) return o;

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