Searched refs:SchedModel (Results 1 - 19 of 19) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h35 MCSchedModel SchedModel; member in class:llvm::TargetSchedModel
67 const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
82 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
85 unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
88 unsigned getILPWindow() const { return SchedModel.ILPWindow; }
96 return SchedModel.getNumProcResourceKinds();
101 return SchedModel.getProcResource(PIdx);
H A DScheduleDAGInstrs.h79 TargetSchedModel SchedModel; member in class:llvm::ScheduleDAGInstrs
150 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
155 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
H A DMachineTraceMetrics.h73 TargetSchedModel SchedModel; member in class:llvm::MachineTraceMetrics
/external/llvm/lib/CodeGen/
H A DTargetSchedule.cpp32 return EnableSchedModel && SchedModel.hasInstrSchedModel();
57 SchedModel = sm;
62 unsigned NumRes = SchedModel.getNumProcResourceKinds();
64 ResourceLCM = SchedModel.IssueWidth;
66 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
70 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth;
72 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
111 if (SchedModel.MinLatency < 0 && !hasInstrItineraries()) {
114 return SchedModel.MinLatency;
117 return TII->defaultDefLatency(&SchedModel, DefM
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H A DMachineScheduler.cpp988 const TargetSchedModel *SchedModel);
1012 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
1014 unsigned getMaxRemainingCount(const TargetSchedModel *SchedModel) const {
1015 if (!SchedModel->hasInstrSchedModel())
1019 RemainingMicroOps * SchedModel->getMicroOpFactor(),
1029 const TargetSchedModel *SchedModel; member in struct:__anon9484::ConvergingScheduler::SchedBoundary
1095 DAG(0), SchedModel(0), Rem(0), Available(ID, Name+".A"),
1141 const TargetSchedModel *SchedModel; member in class:__anon9484::ConvergingScheduler
1158 DAG(0), SchedModel(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
1201 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) { argument
1648 initResourceDelta(const ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) argument
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H A DTargetInstrInfo.cpp622 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel *SchedModel, argument
627 return SchedModel->LoadLatency;
629 return SchedModel->HighLatency;
683 if (ItinData->SchedModel->MinLatency >= 0)
692 return defaultDefLatency(ItinData->SchedModel, DefMI);
737 defaultDefLatency(ItinData->SchedModel, DefMI));
H A DMachineTraceMetrics.cpp58 SchedModel.init(*ST.getSchedModel(), &ST, TII);
749 DepCycle += MTM.SchedModel
774 const TargetSchedModel &SchedModel,
797 // live-in list. SchedModel can handle a NULL UseMI.
798 DepHeight += SchedModel
833 const TargetSchedModel &SchedModel,
837 UseHeight += SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp,
952 Heights, MTM.SchedModel, MTM.TII))
981 MTM.SchedModel, MTM.TII, MTM.TRI);
985 if (pushDepHeight(Deps[i], MI, Cycle, Heights, MTM.SchedModel, MT
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H A DScoreboardHazardRecognizer.cpp79 // A nonempty itinerary must have a SchedModel.
80 IssueWidth = ItinData->SchedModel->IssueWidth;
H A DScheduleDAGInstrs.cpp58 SchedModel.init(*ST.getSchedModel(), &ST, TII);
268 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
272 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
311 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr());
389 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr());
427 SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, false));
429 SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, true));
684 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
H A DEarlyIfConversion.cpp582 const MCSchedModel *SchedModel; member in class:__anon9454::EarlyIfConverter
690 unsigned CritLimit = SchedModel->MispredictPenalty/2;
780 SchedModel =
/external/llvm/include/llvm/MC/
H A DMCInstrItineraries.h113 const MCSchedModel *SchedModel; ///< Basic machine properties. member in class:llvm::InstrItineraryData
121 InstrItineraryData() : SchedModel(&MCSchedModel::DefaultSchedModel),
127 : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F),
128 Itineraries(SchedModel->InstrItineraries) {}
170 return SchedModel->MinLatency < 0 ? 1 : SchedModel->MinLatency;
/external/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.h48 const TargetSchedModel *SchedModel; member in class:llvm::VLIWResourceModel
59 SchedModel(SM), TotalPackets(0) {
66 Packet.resize(SchedModel->getIssueWidth());
135 const TargetSchedModel *SchedModel; member in struct:llvm::ConvergingVLIWScheduler::SchedBoundary
156 DAG(0), SchedModel(0), Available(ID, Name+".A"),
169 SchedModel = smodel;
192 const TargetSchedModel *SchedModel; member in class:llvm::ConvergingVLIWScheduler
208 DAG(0), SchedModel(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
H A DHexagonMachineScheduler.cpp130 if (Packet.size() >= SchedModel->getIssueWidth()) {
197 SchedModel = DAG->getSchedModel();
200 Top.init(DAG, SchedModel);
201 Bot.init(DAG, SchedModel);
272 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
273 if (IssueCount + uops > SchedModel->getIssueWidth())
295 unsigned Width = SchedModel->getIssueWidth();
338 IssueCount += SchedModel->getNumMicroOps(SU->getInstr());
/external/llvm/include/llvm/Target/
H A DTargetSubtargetInfo.h54 const TargetSchedModel* SchedModel) const {
H A DTargetInstrInfo.h835 unsigned defaultDefLatency(const MCSchedModel *SchedModel,
/external/llvm/lib/MC/
H A DMCSubtargetInfo.cpp104 assert(Found->Value && "Missing processor SchedModel value");
110 const MCSchedModel *SchedModel = getSchedModelForCPU(CPU); local
111 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
/external/llvm/lib/Target/ARM/
H A DARMSubtarget.cpp136 SchedModel = getSchedModelForCPU(CPUString);
221 return SchedModel->MispredictPenalty;
H A DARMSubtarget.h172 /// SchedModel - Processor specific instruction costs.
173 const MCSchedModel *SchedModel; member in class:llvm::ARMSubtarget
/external/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp321 if (Packet.size() >= InstrItins->SchedModel->IssueWidth) {

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