Searched refs:XCore (Results 1 - 11 of 11) sorted by relevance
/external/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 1 //===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===// 10 // This file contains the XCore implementation of the MRegisterInfo class. 15 #include "XCore.h" 41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) { 65 XCore::R4, XCore::R5, XCore::R6, XCore::R7, 66 XCore::R8, XCore [all...] |
H A D | XCoreInstrInfo.cpp | 1 //===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===// 10 // This file contains the XCore implementation of the TargetInstrInfo class. 15 #include "XCore.h" 29 namespace XCore { namespace in namespace:llvm 31 // XCore Condition Codes 43 : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), 59 if (Opcode == XCore::LDWFI) 81 if (Opcode == XCore::STWFI) 99 return BrOpc == XCore [all...] |
H A D | XCoreFrameLowering.cpp | 1 //===-- XCoreFrameLowering.cpp - Frame info for XCore Target --------------===// 10 // This file contains XCore frame information that doesn't fit anywhere else 16 #include "XCore.h" 54 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; 69 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6; 104 loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII); 125 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore [all...] |
H A D | Makefile | 1 ##===- lib/Target/XCore/Makefile ---------------------------*- Makefile -*-===## 12 TARGET = XCore
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H A D | XCoreISelDAGToDAG.cpp | 1 //===-- XCoreISelDAGToDAG.cpp - A dag to dag inst selector for XCore ------===// 10 // This file defines an instruction selector for the XCore target. 14 #include "XCore.h" 35 /// XCoreDAGToDAGISel - XCore specific code to select XCore machine 75 return "XCore DAG->DAG Pattern Instruction Selection"; 84 /// XCore-specific DAG, ready for instruction scheduling. 165 return CurDAG->getMachineNode(XCore::MKMSK_rus, dl, 173 SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, 187 return CurDAG->getMachineNode(XCore [all...] |
H A D | XCoreAsmPrinter.cpp | 1 //===-- XCoreAsmPrinter.cpp - XCore LLVM assembly writer ------------------===// 11 // of machine-dependent LLVM code to the XAS-format XCore assembly language. 16 #include "XCore.h" 66 return "XCore Assembly Printer"; 302 case XCore::DBG_VALUE: { 311 case XCore::ADD_2rus: 320 case XCore::BR_JT: 321 case XCore::BR_JT32: 324 if (MI->getOpcode() == XCore::BR_JT)
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H A D | XCoreISelLowering.cpp | 1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===// 17 #include "XCore.h" 70 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); 78 setStackPointerRegisterToSaveRestore(XCore::SP); 86 // XCore does not have the NodeTypes below. 893 /// XCore call implementation 908 // XCore target does not yet support tail call optimization. 1082 /// XCore formal arguments implementation 1148 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); 1179 XCore [all...] |
/external/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===// 11 /// \brief This file is part of the XCore Disassembler. 15 #include "XCore.h" 30 /// \brief A disassembler class for XCore. 212 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo); 276 Inst.setOpcode(XCore::STW_2rus); 279 Inst.setOpcode(XCore::LDW_2rus); 282 Inst.setOpcode(XCore::ADD_3r); 285 Inst.setOpcode(XCore::SUB_3r); 288 Inst.setOpcode(XCore [all...] |
/external/llvm/lib/Target/XCore/MCTargetDesc/ |
H A D | XCoreMCTargetDesc.cpp | 1 //===-- XCoreMCTargetDesc.cpp - XCore Target Descriptions -----------------===// 10 // This file provides XCore specific target descriptions. 43 InitXCoreMCRegisterInfo(X, XCore::LR); 59 MachineLocation Src(XCore::SP, 0);
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/external/llvm/ |
H A D | configure | 4017 xcore-*) llvm_cv_target_arch="XCore" ;; 4051 xcore-*) host_arch="XCore" ;; 5385 XCore) TARGET_HAS_JIT=0 5604 all) TARGETS_TO_BUILD="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend MBlaze NVPTX Hexagon" ;; 5617 xcore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;; 5631 XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
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/external/llvm/projects/sample/ |
H A D | configure | 3850 xcore-*) llvm_cv_target_arch="XCore" ;; 5109 XCore) TARGET_HAS_JIT=0 5303 all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM AArch64 Mips XCore MSP430 Hexagon CppBackend MBlaze NVPTX" ;; 5313 xcore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;; 5328 XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
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