| /external/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 73 unsigned Reg, unsigned Lane,
79 unsigned DReg, unsigned Lane,
94 DebugLoc DL, unsigned DReg, unsigned Lane,
434 unsigned Reg, unsigned Lane, bool QPR) {
443 .addImm(Lane));
453 unsigned DReg, unsigned Lane,
460 .addReg(DReg, 0, Lane);
504 DebugLoc DL, unsigned DReg, unsigned Lane,
513 .addImm(Lane);
567 unsigned Lane; local
431 createDupLane(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned Reg, unsigned Lane, bool QPR) argument
450 createExtractSubreg(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned DReg, unsigned Lane, const TargetRegisterClass *TRC) argument
502 createInsertSubreg(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned DReg, unsigned Lane, unsigned ToInsert) argument
[all...] |
| H A D | ARMExpandPseudoInsts.cpp | 505 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); local
509 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
511 Lane -= RegElts;
513 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
558 MIB.addImm(Lane);
1010 unsigned Lane = TRI->getEncodingValue(SrcReg) & 1; local
1012 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0,
1020 MIB.addImm(Lane);
|
| H A D | ARMBaseInstrInfo.cpp | 3763 unsigned SReg, unsigned &Lane) {
3765 Lane = 0;
3770 Lane = 1;
3785 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
3786 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
3794 unsigned DReg, unsigned Lane,
3805 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
3823 unsigned Lane; local
3862 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
3864 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 1
3762 getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, unsigned SReg, unsigned &Lane) argument
3792 getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, MachineInstr *MI, unsigned DReg, unsigned Lane, unsigned &ImplicitSReg) argument
[all...] |
| H A D | ARMCodeEmitter.cpp | 1977 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1978 unsigned Opc1 = Lane >> 2;
1979 unsigned Opc2 = Lane & 3;
|
| H A D | ARMISelLowering.cpp | 4869 int Lane = SVN->getSplatIndex(); local
4871 if (Lane == -1) Lane = 0;
4874 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4880 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
4892 DAG.getConstant(Lane, MVT::i32));
5002 SDValue Lane = Op.getOperand(2); local
5003 if (!isa<ConstantSDNode>(Lane))
5011 SDValue Lane = Op.getOperand(1); local
5012 if (!isa<ConstantSDNode>(Lane))
9218 SDValue Lane = N0.getOperand(1); local
[all...] |
| H A D | ARMISelDAGToDAG.cpp | 1983 unsigned Lane = local
2059 Ops.push_back(getI32Imm(Lane));
|
| /external/jpeg/ |
| H A D | jmemdosa.asm | 4 ; Copyright (C) 1992, Thomas G. Lane.
|
| /external/qemu/distrib/jpeg-6b/ |
| H A D | jmemdosa.asm | 4 ; Copyright (C) 1992, Thomas G. Lane.
|
| /external/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 1945 int Lane = cast<ConstantInt>(Ops[2])->getZExtValue(); local
1946 Value *SV = llvm::ConstantVector::get(ConstantInt::get(Int32Ty, 1-Lane));
1954 Indices.push_back(ConstantInt::get(Int32Ty, 1-Lane));
1955 Indices.push_back(ConstantInt::get(Int32Ty, Lane));
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1200 const MCExpr *Lane = MCConstantExpr::Create(Parser.getTok().getIntVal(), local
1205 Operands.push_back(AArch64Operand::CreateImm(Lane, S, E));
|