Searched refs:isSub (Results 1 - 11 of 11) sorted by relevance

/external/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp182 bool isSub = NumBytes < 0;
183 if (isSub) NumBytes = -NumBytes;
207 if (isSub) {
240 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
248 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
261 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
265 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
394 bool isSub = false;
420 isSub = true;
439 unsigned NewOpc = isSub
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H A DThumb1RegisterInfo.cpp101 bool isSub = false; local
107 isSub = true;
129 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
134 if (DestReg == ARM::SP || isSub)
174 bool isSub = NumBytes < 0; local
176 if (isSub) Bytes = -NumBytes;
190 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
192 } else if (!isSub && BaseReg == ARM::SP) {
212 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
217 Opc = isSub
307 bool isSub = Imm < 0; local
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H A DARMBaseInstrInfo.cpp166 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; local
174 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
181 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
186 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
192 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; local
197 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
202 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
1779 bool isSub = NumBytes < 0; local
1780 if (isSub) NumBytes = -NumBytes;
1793 unsigned Opc = isSub
2399 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; local
2415 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; local
2443 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; local
2456 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; local
2508 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; local
3132 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; local
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H A DARMISelLowering.cpp7034 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; local
7036 if (isSub)
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h410 bool isSub = Opc == sub;
411 return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
444 bool isSub = Opc == sub;
445 return ((int)isSub << 8) | Offset | (IdxMode << 9);
493 bool isSub = Opc == sub;
494 return ((int)isSub << 8) | Offset;
/external/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp150 bool isSub = NumBytes < 0; local
151 uint64_t Offset = isSub ? -NumBytes : NumBytes;
156 Opc = isSub
167 unsigned Reg = isSub
171 Opc = isSub
175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
176 if (isSub)
187 StackPtr, false, isSub ? -ThisVal : ThisVal);
195 if (isSub)
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/external/llvm/lib/Transforms/InstCombine/
H A DInstCombine.h368 bool isSub, Instruction &I);
H A DInstCombineAndOrXor.cpp335 /// where isSub determines whether the operator is a sub. If we can fold one of
345 ConstantInt *Mask, bool isSub,
385 if (isSub)
344 FoldLogicalPlusAnd(Value *LHS, Value *RHS, ConstantInt *Mask, bool isSub, Instruction &I) argument
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp1039 bool isSub = OffImm < 0;
1043 if (isSub) {
/external/clang/lib/CodeGen/
H A DCGExprScalar.cpp2325 bool isSub=false) {
2345 return buildFMulAdd(LHSBinOp, op.RHS, CGF, Builder, false, isSub);
2352 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub, false);
2323 tryEmitFMulAdd(const BinOpInfo &op, const CodeGenFunction &CGF, CGBuilderTy &Builder, bool isSub=false) argument
/external/valgrind/main/VEX/priv/
H A Dguest_arm_toIR.c15977 UInt isSub = INSN0(9,9); local
15982 putIRegT(rD, binop(isSub ? Iop_Sub32 : Iop_Add32,
15985 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD,
15987 DIP("%s r%u, r%u, #%u\n", isSub ? "subs" : "adds", rD, rN, uimm3);
15998 UInt isSub = INSN0(9,9); local
16003 putIRegT( rD, binop(isSub ? Iop_Sub32 : Iop_Add32,
16006 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD,
16008 DIP("%s r%u, r%u, r%u\n", isSub ? "subs" : "adds", rD, rN, rM);
16151 UInt isSub = INSN0(11,11); local
16158 putIRegT( rN, binop(isSub
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