1//=======- NVPTXFrameLowering.cpp - NVPTX Frame Information ---*- C++ -*-=====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the NVPTX implementation of TargetFrameLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "NVPTXFrameLowering.h"
15#include "NVPTX.h"
16#include "NVPTXRegisterInfo.h"
17#include "NVPTXSubtarget.h"
18#include "NVPTXTargetMachine.h"
19#include "llvm/ADT/BitVector.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/MC/MachineLocation.h"
24#include "llvm/Target/TargetInstrInfo.h"
25
26using namespace llvm;
27
28bool NVPTXFrameLowering::hasFP(const MachineFunction &MF) const {
29  return true;
30}
31
32void NVPTXFrameLowering::emitPrologue(MachineFunction &MF) const {
33  if (MF.getFrameInfo()->hasStackObjects()) {
34    MachineBasicBlock &MBB = MF.front();
35    // Insert "mov.u32 %SP, %Depot"
36    MachineBasicBlock::iterator MBBI = MBB.begin();
37    // This instruction really occurs before first instruction
38    // in the BB, so giving it no debug location.
39    DebugLoc dl = DebugLoc();
40
41    if (tm.getSubtargetImpl()->hasGenericLdSt()) {
42      // mov %SPL, %depot;
43      // cvta.local %SP, %SPL;
44      if (is64bit) {
45        MachineInstr *MI = BuildMI(MBB, MBBI, dl,
46                               tm.getInstrInfo()->get(NVPTX::cvta_local_yes_64),
47                                   NVPTX::VRFrame).addReg(NVPTX::VRFrameLocal);
48        BuildMI(MBB, MI, dl,
49                tm.getInstrInfo()->get(NVPTX::IMOV64rr), NVPTX::VRFrameLocal)
50        .addReg(NVPTX::VRDepot);
51      } else {
52        MachineInstr *MI = BuildMI(MBB, MBBI, dl,
53                                  tm.getInstrInfo()->get(NVPTX::cvta_local_yes),
54                                   NVPTX::VRFrame).addReg(NVPTX::VRFrameLocal);
55        BuildMI(MBB, MI, dl,
56                tm.getInstrInfo()->get(NVPTX::IMOV32rr), NVPTX::VRFrameLocal)
57        .addReg(NVPTX::VRDepot);
58      }
59    }
60    else {
61      // mov %SP, %depot;
62      if (is64bit)
63        BuildMI(MBB, MBBI, dl,
64                tm.getInstrInfo()->get(NVPTX::IMOV64rr), NVPTX::VRFrame)
65                .addReg(NVPTX::VRDepot);
66      else
67        BuildMI(MBB, MBBI, dl,
68                tm.getInstrInfo()->get(NVPTX::IMOV32rr), NVPTX::VRFrame)
69                .addReg(NVPTX::VRDepot);
70    }
71  }
72}
73
74void NVPTXFrameLowering::emitEpilogue(MachineFunction &MF,
75                                      MachineBasicBlock &MBB) const {
76}
77
78// This function eliminates ADJCALLSTACKDOWN,
79// ADJCALLSTACKUP pseudo instructions
80void NVPTXFrameLowering::
81eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
82                              MachineBasicBlock::iterator I) const {
83  // Simply discard ADJCALLSTACKDOWN,
84  // ADJCALLSTACKUP instructions.
85  MBB.erase(I);
86}
87
88