/external/valgrind/main/memcheck/tests/amd64-linux/ |
H A D | int3-amd64.stdout.exp | 2 in int_handler, RIP is ...
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/external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/tests/ |
H A D | riprel1.asm | 45 mov rax, [val] ; 48 8b ... (32-bit disp, RIP-rel) 46 mov rax, [dword val] ; 48 8b ... (32-bit disp, RIP-rel) 48 a32 mov rax, [val] ; 67 48 8b ... (32-bit disp, RIP-rel) 49 a32 mov rax, [dword val] ; 67 48 8b ... (32-bit disp, RIP-rel) 53 a64 mov rax, [val] ; 48 8b ... (32-bit disp, RIP-rel) 54 a64 mov rax, [dword val] ; 48 8b ... (32-bit disp, RIP-rel) 57 mov rbx, [val] ; 48 8b ... (32-bit disp, RIP-rel) 58 mov rbx, [dword val] ; 48 8b ... (32-bit disp, RIP-rel) 60 a32 mov rbx, [val] ; 67 48 8b ... (32-bit disp, RIP-rel) 61 a32 mov rbx, [dword val] ; 67 48 8b ... (32-bit disp, RIP [all...] |
/external/kernel-headers/original/asm-x86/ |
H A D | ptrace-abi.h | 47 #define RIP 128 macro
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCTargetDesc.cpp | 254 ? X86::RIP // Should have dwarf #16. 299 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
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H A D | X86AsmBackend.cpp | 239 // Check if it has an expression and is not RIP relative. 247 if (Op.isReg() && Op.getReg() == X86::RIP)
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H A D | X86MCCodeEmitter.cpp | 378 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode 406 // If no BaseReg, issue a RIP relative instruction only if the MCE can 417 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
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/external/valgrind/main/VEX/auxprogs/ |
H A D | genoffsets.c | 116 GENOFFSET(AMD64,amd64,RIP);
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/external/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 59 ? X86::RIP : X86::EIP), 63 ? X86::RIP : X86::EIP)), 323 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
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H A D | X86CodeEmitter.cpp | 432 // But it's probably not beneficial. If the MCE supports using RIP directly 487 if (BaseReg == X86::RIP || 488 (Is64BitMode && DispForReloc)) { // [disp32+RIP] in X86-64 mode 498 // while others, unless explicit asked to use RIP, use absolute references. 502 // If no BaseReg, issue a RIP relative instruction only if the MCE can 506 if (BaseReg != 0 && BaseReg != X86::RIP) 516 // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 519 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
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H A D | X86AsmPrinter.cpp | 279 BaseReg.getReg() == X86::RIP)
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H A D | X86FastISel.cpp | 512 // RIP-relative addresses can't have additional register operands, so if 536 AM.Base.Reg = X86::RIP; 565 StubAM.Base.Reg = X86::RIP; 645 // RIP-relative addresses can't have additional register operands. 668 AM.Base.Reg = X86::RIP; 2405 PICBase = X86::RIP;
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H A D | X86MCInstLower.cpp | 646 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
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H A D | X86ISelDAGToDAG.cpp | 85 /// isRIPRelative - Return true if this addressing mode is already RIP 91 return RegNode->getReg() == X86::RIP; 236 // These are 32-bit even in 64-bit mode since RIP relative offset 642 // folding because RIP is preferable to non-RIP accesses. 686 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64)); 692 // mode, this only applies to a non-RIP-relative computation. 696 "RIP-relative addressing already handled"); 751 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64); 976 // RIP relativ [all...] |
H A D | X86InstrInfo.cpp | 1592 if (BaseReg == 0 || BaseReg == X86::RIP) 4130 PICBase = X86::RIP; 4838 "X86-64 PIC uses RIP relative addressing"); 5028 "X86-64 PIC uses RIP relative addressing");
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H A D | X86ISelLowering.cpp | 1698 // X86-64 uses RIP relative addressing based on the jump table label. 8117 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 14928 .addReg(X86::RIP) 15043 .addReg(X86::RIP) 18928 // RIP in the class. Do they matter any more here than they do
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/external/llvm/lib/Transforms/ObjCARC/ |
H A D | ObjCARCOpts.cpp | 2556 Instruction *RIP = *RI; local 2557 if (ReleasesToMove.ReverseInsertPts.insert(RIP)) { 2560 const BBState &RIPBBState = BBStates[RIP->getParent()]; 2610 Instruction *RIP = *RI; local 2611 if (RetainsToMove.ReverseInsertPts.insert(RIP)) { 2614 const BBState &RIPBBState = BBStates[RIP->getParent()];
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/external/llvm/lib/Target/X86/Disassembler/ |
H A D | X86DisassemblerDecoder.h | 358 ENTRY(RIP)
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H A D | X86Disassembler.cpp | 470 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
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/external/valgrind/main/coregrind/m_sigframe/ |
H A D | sigframe-amd64-linux.c | 362 SC2(rip,RIP); 529 "next %%RIP = %#llx, status=%d\n", 630 "VG_(signal_return) (thread %d): isRT=%d valid magic; RIP=%#llx\n",
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/external/iproute2/doc/ |
H A D | ip-tunnels.tex | 92 with ttl 1 will reach peering host (f.e.\ RIP, OSPF or EBGP)
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/external/strace/ |
H A D | util.c | 1099 if (upeek(tcp, 8*RIP, &rip) < 0) {
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H A D | process.c | 2690 { 8*RIP, "8*RIP" },
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H A D | syscall.c | 931 if (upeek(tcp, 8*RIP, &rip) < 0) 932 perror("upeek(RIP)");
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/external/valgrind/main/memcheck/ |
H A D | mc_machine.c | 588 if (o == GOF(RIP) && sz == 8) return -1; /* slot unused */
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