/external/llvm/lib/MC/ |
H A D | MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument 21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb2RegisterInfo.cpp | 37 unsigned DestReg, unsigned SubIdx, 49 .addReg(DestReg, getDefRegState(true), SubIdx) 34 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | Thumb1RegisterInfo.cpp | 67 unsigned DestReg, unsigned SubIdx, 79 .addReg(DestReg, getDefRegState(true), SubIdx) 64 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | ARMBaseRegisterInfo.cpp | 388 unsigned DestReg, unsigned SubIdx, int Val, 399 .addReg(DestReg, getDefRegState(true), SubIdx) 385 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | ARMBaseInstrInfo.cpp | 746 unsigned SubIdx, unsigned State, 748 if (!SubIdx) 752 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 753 return MIB.addReg(Reg, State, SubIdx); 1252 unsigned DestReg, unsigned SubIdx, 1259 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 745 AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const argument 1250 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const argument
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H A D | ARMISelDAGToDAG.cpp | 2199 unsigned SubIdx = ARM::dsub_0; local 2202 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
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/external/llvm/lib/CodeGen/ |
H A D | ExpandPostRAPseudos.cpp | 87 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); 88 unsigned SubIdx = MI->getOperand(3).getImm(); local 90 assert(SubIdx != 0 && "Invalid index for insert_subreg"); 91 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); 113 MI->RemoveOperand(3); // SubIdx
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H A D | MachineCopyPropagation.cpp | 120 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); local 121 if (!SubIdx) 123 return SubIdx == TRI->getSubRegIndex(SrcDef, Src);
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H A D | PeepholeOptimizer.cpp | 150 unsigned SrcReg, DstReg, SubIdx; local 151 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) 165 DstRC = TM->getRegisterInfo()->getSubClassWithSubReg(DstRC, SubIdx); 172 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of 173 // SrcReg:SubIdx should be replaced. 175 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0; 205 // Only accept uses of SrcReg:SubIdx. 206 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) 286 .addReg(DstReg, 0, SubIdx); 287 // SubIdx applie [all...] |
H A D | TargetRegisterInfo.cpp | 47 if (SubIdx) { 49 OS << ':' << TRI->getSubRegIndexName(SubIdx); 51 OS << ":sub(" << SubIdx << ')'; local
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H A D | TargetInstrInfo.cpp | 282 unsigned SubIdx, 286 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); 279 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const argument
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H A D | MachineVerifier.cpp | 889 unsigned SubIdx = MO->getSubReg(); local 892 if (SubIdx) { 907 if (SubIdx) { 909 TRI->getSubClassWithSubReg(RC, SubIdx); 913 << " does not support subreg index " << SubIdx << "\n"; 919 << " does not fully support subreg index " << SubIdx << "\n"; 925 if (SubIdx) { 932 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
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H A D | TwoAddressInstructionPass.cpp | 1571 unsigned SubIdx = mi->getOperand(3).getImm(); local 1574 mi->getOperand(0).setSubReg(SubIdx); 1627 unsigned SubIdx = MI->getOperand(i+1).getImm(); local 1647 .addReg(DstReg, RegState::Define, SubIdx)
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H A D | MachineInstr.cpp | 69 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, argument 72 if (SubIdx && getSubReg()) 73 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); 75 if (SubIdx) 76 setSubReg(SubIdx); 1201 unsigned SubIdx, 1204 if (SubIdx) 1205 ToReg = RegInfo.getSubReg(ToReg, SubIdx); 1217 MO.substVirtReg(ToReg, SubIdx, RegInf 1199 substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo) argument [all...] |
H A D | RegisterCoalescer.cpp | 180 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx); 335 "Cannot have a physical SubIdx"); 944 unsigned SubIdx) { 965 if (DstInt && !Reads && SubIdx) 975 if (SubIdx && MO.isDef()) 981 MO.substVirtReg(DstReg, SubIdx, *TRI); 1283 unsigned SubIdx; member in class:__anon22128::JoinVals 1389 : LI(li), SubIdx(subIdx), NewVNInfo(newVNInfo), CP(cp), LIS(lis), 1428 TRI->composeSubRegIndices(SubIdx, MO->getSubReg())); 1474 V.ValidLanes = V.WriteLanes = TRI->getSubRegIndexLaneMask(SubIdx); 942 updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx) argument 1769 usesLanes(MachineInstr *MI, unsigned Reg, unsigned SubIdx, unsigned Lanes) argument [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetRegisterInfo.h | 336 const char *getSubRegIndexName(unsigned SubIdx) const { 337 assert(SubIdx && SubIdx < getNumSubRegIndices() && 339 return SubRegIndexNames[SubIdx-1]; 343 /// register that are covered by SubIdx. 361 unsigned getSubRegIndexLaneMask(unsigned SubIdx) const { 362 // SubIdx == 0 is allowed, it has the lane mask ~0u. 363 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); 364 return SubRegIndexLaneMasks[SubIdx]; 456 /// Reg so its sub-register of index SubIdx i 881 unsigned SubIdx; member in class:llvm::TargetRegisterInfo::PrintReg [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 411 unsigned SubIdx = (IsI64 ? Mips::sub_32 : Mips::sub_fpeven); local 417 TmpReg = getRegisterInfo().getSubReg(DstReg, SubIdx); 420 DstReg = getRegisterInfo().getSubReg(DstReg, SubIdx); 435 unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven; 436 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 88 unsigned &SubIdx) const { 95 SubIdx = PPC::sub_32; 494 unsigned SubIdx; local 498 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break; 499 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break; 500 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break; 501 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break; 502 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break; 503 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break; 504 case PPC::PRED_UN: SubIdx 1157 unsigned SubIdx = UseMI->getOperand(3).getSubReg(); local [all...] |
/external/llvm/lib/Target/R600/ |
H A D | SIISelLowering.cpp | 714 int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); local 717 return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
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/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.h | 315 // registers have a SubIdx sub-register. 317 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const { 318 return SubClassWithSubReg.lookup(SubIdx); 321 void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx, argument 323 SubClassWithSubReg[SubIdx] = SubRC; 327 // containing only SubIdx super-registers of this class. 328 void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const; 331 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, argument 333 SuperRegClasses[SubIdx].insert(SuperRC);
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H A D | AsmMatcherEmitter.cpp | 1626 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second; local 1633 int SrcOperand = findAsmOperand(Name, SubIdx); 1638 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
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H A D | CodeGenRegisters.cpp | 480 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); local 481 if (!SubIdx) 484 NewIdx->addComposite(SI->first, SubIdx); 506 // Topological signature computed from SubIdx, TopoId(SubReg). 899 CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx, argument 903 FindI = SuperRegClasses.find(SubIdx); 1495 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); 1496 SubIdx != EndIdx; ++SubIdx) { 1497 const RegUnitSet &SubSet = RegUnitSets[SubIdx]; 1807 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri]; local 1840 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri]; local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 1373 unsigned &SubIdx) const { 1401 SubIdx = X86::sub_8bit; 1406 SubIdx = X86::sub_16bit; 1409 SubIdx = X86::sub_32bit; 1713 unsigned DestReg, unsigned SubIdx, 1729 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1711 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const argument
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