1//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
11          : Instruction {
12  field bits<32> Inst;
13
14  let Namespace = "SP";
15
16  bits<2> op;
17  let Inst{31-30} = op;               // Top two bits are the 'op' field
18
19  dag OutOperandList = outs;
20  dag InOperandList = ins;
21  let AsmString   = asmstr;
22  let Pattern = pattern;
23}
24
25//===----------------------------------------------------------------------===//
26// Format #2 instruction classes in the Sparc
27//===----------------------------------------------------------------------===//
28
29// Format 2 instructions
30class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
31   : InstSP<outs, ins, asmstr, pattern> {
32  bits<3>  op2;
33  bits<22> imm22;
34  let op          = 0;    // op = 0
35  let Inst{24-22} = op2;
36  let Inst{21-0}  = imm22;
37}
38
39// Specific F2 classes: SparcV8 manual, page 44
40//
41class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
42   : F2<outs, ins, asmstr, pattern> {
43  bits<5>  rd;
44
45  let op2         = op2Val;
46
47  let Inst{29-25} = rd;
48}
49
50class F2_2<bits<4> condVal, bits<3> op2Val, dag outs, dag ins, string asmstr,
51           list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
52  bits<4>   cond;
53  bit       annul = 0;     // currently unused
54
55  let cond        = condVal;
56  let op2         = op2Val;
57
58  let Inst{29}    = annul;
59  let Inst{28-25} = cond;
60}
61
62//===----------------------------------------------------------------------===//
63// Format #3 instruction classes in the Sparc
64//===----------------------------------------------------------------------===//
65
66class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
67    : InstSP<outs, ins, asmstr, pattern> {
68  bits<5> rd;
69  bits<6> op3;
70  bits<5> rs1;
71  let op{1} = 1;   // Op = 2 or 3
72  let Inst{29-25} = rd;
73  let Inst{24-19} = op3;
74  let Inst{18-14} = rs1;
75}
76
77// Specific F3 classes: SparcV8 manual, page 44
78//
79class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
80           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
81  bits<8> asi = 0; // asi not currently used
82  bits<5> rs2;
83
84  let op         = opVal;
85  let op3        = op3val;
86
87  let Inst{13}   = 0;     // i field = 0
88  let Inst{12-5} = asi;   // address space identifier
89  let Inst{4-0}  = rs2;
90}
91
92class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
93           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
94  bits<13> simm13;
95
96  let op         = opVal;
97  let op3        = op3val;
98
99  let Inst{13}   = 1;     // i field = 1
100  let Inst{12-0} = simm13;
101}
102
103// floating-point
104class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
105           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
106  bits<5> rs2;
107
108  let op         = opVal;
109  let op3        = op3val;
110
111  let Inst{13-5} = opfval;   // fp opcode
112  let Inst{4-0}  = rs2;
113}
114
115// Shift by register rs2.
116class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
117            string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
118  bit x = xVal;           // 1 for 64-bit shifts.
119  bits<5> rs2;
120
121  let op         = opVal;
122  let op3        = op3val;
123
124  let Inst{13}   = 0;     // i field = 0
125  let Inst{12}   = x;     // extended registers.
126  let Inst{4-0}  = rs2;
127}
128
129// Shift by immediate.
130class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
131            string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
132  bit x = xVal;           // 1 for 64-bit shifts.
133  bits<6> shcnt;          // shcnt32 / shcnt64.
134
135  let op         = opVal;
136  let op3        = op3val;
137
138  let Inst{13}   = 1;     // i field = 1
139  let Inst{12}   = x;     // extended registers.
140  let Inst{5-0}  = shcnt;
141}
142
143// Define rr and ri shift instructions with patterns.
144multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
145                ValueType VT, RegisterClass RC> {
146  def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, IntRegs:$rs2),
147                 !strconcat(OpcStr, " $rs, $rs2, $rd"),
148                 [(set VT:$rd, (OpNode VT:$rs, i32:$rs2))]>;
149  def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, i32imm:$shcnt),
150                 !strconcat(OpcStr, " $rs, $shcnt, $rd"),
151                 [(set VT:$rd, (OpNode VT:$rs, (i32 imm:$shcnt)))]>;
152}
153