SparcInstrFormats.td revision 13e1501c91e3e56740a59eb7dab173c1d0cf5765 
1//===- SparcV8InstrFormats.td - SparcV8 Instr Formats ------*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Format #2 instruction classes in the SparcV8
12//===----------------------------------------------------------------------===//
13
14class F2 : InstV8 {                   // Format 2 instructions
15  bits<3>  op2;
16  bits<22> imm22;
17  let op          = 0;    // op = 0
18  let Inst{24-22} = op2;
19  let Inst{21-0}  = imm22;
20}
21
22// Specific F2 classes: SparcV8 manual, page 44
23//
24class F2_1<bits<3> op2Val, dag ops, string asmstr> : F2 {
25  bits<5>  rd;
26
27  dag OperandList = ops;
28  let AsmString   = asmstr;
29
30  let op2         = op2Val;
31
32  let Inst{29-25} = rd;
33}
34
35class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
36  bits<4>   cond;
37  bit       annul = 0;     // currently unused
38
39  let cond        = condVal;
40  let op2         = op2Val;
41  let Name        = name;
42
43  let Inst{29}    = annul;
44  let Inst{28-25} = cond;
45}
46
47//===----------------------------------------------------------------------===//
48// Format #3 instruction classes in the SparcV8
49//===----------------------------------------------------------------------===//
50
51class F3 : InstV8 {
52  bits<5> rd;
53  bits<6> op3;
54  bits<5> rs1;
55  let op{1} = 1;   // Op = 2 or 3
56  let Inst{29-25} = rd;
57  let Inst{24-19} = op3;
58  let Inst{18-14} = rs1;
59}
60
61// Specific F3 classes: SparcV8 manual, page 44
62//
63class F3_1<bits<2> opVal, bits<6> op3val, dag ops, string asmstr> : F3 {
64  bits<8> asi = 0; // asi not currently used in SparcV8
65  bits<5> rs2;
66
67  dag OperandList = ops;
68  let AsmString   = asmstr;
69
70  let op         = opVal;
71  let op3        = op3val;
72
73  let Inst{13}   = 0;     // i field = 0
74  let Inst{12-5} = asi;   // address space identifier
75  let Inst{4-0}  = rs2;
76}
77
78class F3_2<bits<2> opVal, bits<6> op3val, dag ops, string asmstr> : F3 {
79  bits<13> simm13;
80
81  dag OperandList = ops;
82  let AsmString   = asmstr;
83  
84  let op         = opVal;
85  let op3        = op3val;
86
87  let Inst{13}   = 1;     // i field = 1
88  let Inst{12-0} = simm13;
89}
90
91// floating-point
92class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, string name> : F3 {
93  bits<5> rs2;
94
95  let op         = opVal;
96  let op3        = op3val;
97  let Name       = name;
98
99  let Inst{13-5} = opfval;   // fp opcode
100  let Inst{4-0}  = rs2;
101}
102