Searched defs:Reg0 (Results 1 - 10 of 10) sorted by relevance

/external/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp248 unsigned Reg0 = Op0.getReg(); local
249 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
253 if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
255 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
/external/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp323 unsigned Reg0 = local
329 std::swap(Reg0, Reg1);
332 MCCFIInstruction::createOffset(CSLabel, Reg0, Offset));
/external/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp135 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; local
145 if (HasDef && Reg0 == Reg1 &&
148 Reg0 = Reg2;
150 } else if (HasDef && Reg0 == Reg2 &&
153 Reg0 = Reg1;
164 MI->getOperand(0).setReg(Reg0);
/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp328 unsigned Reg0 = MI->getOperand(0).getReg(); local
331 if (isStackReg(Reg0) || isStackReg(Reg1)) {
334 if (Reg0 == AArch64::XSP || Reg1 == AArch64::XSP)
/external/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp643 unsigned Reg0 = MI->getOperand(0).getReg(); local
649 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
652 if (Reg0 != Reg2) {
655 if (Reg1 != Reg0)
662 } else if (Reg0 != Reg1) {
666 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0)
672 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
H A DARMAsmPrinter.cpp470 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); local
471 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
H A DARMISelDAGToDAG.cpp1782 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
1794 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1802 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1805 Ops.push_back(Reg0);
1818 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1831 Ops.push_back(Reg0);
1835 Ops.push_back(Reg0);
1908 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
1944 // FIXME: VST1/VST2 fixed increment doesn't need Reg0
2071 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2167 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2269 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2699 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2715 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
3557 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); local
[all...]
/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h524 uint16_t Reg0; member in class:llvm::MCRegUnitRootIterator
527 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
530 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
536 return Reg0;
541 return Reg0;
547 Reg0 = Reg1;
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp171 unsigned Reg0 = MI->getOperand(0).getReg(); local
179 if (Reg0 == Reg1) {
193 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); local
196 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1097 SDNode *Reg0 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, local
1101 Even = SDValue(Reg0, 0);

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