Searched defs:SetCC (Results 1 - 12 of 12) sorted by relevance

/external/chromium_org/v8/src/ia32/
H A Ddisasm-ia32.cc361 int SetCC(byte* data);
660 int DisassemblerIA32::SetCC(byte* data) { function in class:disasm::DisassemblerIA32
1095 data += SetCC(data);
/external/llvm/lib/Target/R600/
H A DSIISelLowering.cpp433 SDNode *SetCC = Intr; local
434 assert(SetCC->getConstantOperandVal(1) == 1);
435 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
437 Intr = SetCC->getOperand(0).getNode();
/external/v8/src/ia32/
H A Ddisasm-ia32.cc361 int SetCC(byte* data);
658 int DisassemblerIA32::SetCC(byte* data) { function in class:disasm::DisassemblerIA32
1048 data += SetCC(data);
/external/chromium_org/v8/src/x64/
H A Ddisasm-x64.cc436 int SetCC(byte* data);
834 int DisassemblerX64::SetCC(byte* data) { function in class:disasm::DisassemblerX64
1313 current = data + SetCC(data);
/external/v8/src/x64/
H A Ddisasm-x64.cc431 int SetCC(byte* data);
825 int DisassemblerX64::SetCC(byte* data) { function in class:disasm::DisassemblerX64
1253 current = data + SetCC(data);
/external/chromium_org/v8/src/arm/
H A Dconstants-arm.h238 SetCC = 1 << 20, // Set condition code. enumerator in enum:v8::internal::SBit
H A Dlithium-codegen-arm.cc831 __ sub(r1, r1, Operand(1), SetCC);
1125 __ rsb(result_reg, result_reg, Operand::Zero(), SetCC);
1230 __ sub(result_reg, left_reg, scratch, SetCC);
1269 __ rsb(result, dividend, Operand::Zero(), SetCC);
1368 __ sub(result, dividend, Operand::Zero(), SetCC);
1542 __ eor(remainder, left, Operand(right), SetCC);
1578 __ rsb(result, left, Operand::Zero(), SetCC);
1717 __ mov(result, Operand(left, LSR, scratch), SetCC);
1766 __ SmiTag(result, result, SetCC);
1768 __ SmiTag(result, left, SetCC);
4679 __ SmiTag(ToRegister(output), ToRegister(input), SetCC); local
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp494 // Promote all the way up to the canonical SetCC type.
536 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS, local
541 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
894 // Promote all the way up to the canonical SetCC type.
987 // Promote all the way up to the canonical SetCC type.
H A DDAGCombiner.cpp575 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
3461 llvm_unreachable("Unhandled SetCC Equivalent!");
4373 // Extend SetCC uses if necessary.
4375 SDNode *SetCC = SetCCs[i]; local
4379 SDValue SOp = SetCC->getOperand(j);
4386 Ops.push_back(SetCC->getOperand(2));
4387 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
6857 SDValue SetCC = local
6864 MVT::Other, Chain, SetCC, N
6930 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor), local
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1807 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS, local
1810 Chain, SetCC, A64cc, DestBB);
1815 A64BR_CC, SetCC, A64cc, DestBB);
2252 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS, local
2256 SetCC, IfTrue, IfFalse, A64cc);
2261 SetCC, IfTrue, A64SELECT_CC, A64cc);
/external/v8/src/arm/
H A Dconstants-arm.h273 SetCC = 1 << 20, // Set condition code. enumerator in enum:v8::internal::SBit
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp9848 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
10847 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, local
10849 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11144 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); local
11145 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11300 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, local
11303 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11429 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, local
11432 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
12483 SDValue SetCC local
12496 SDValue SetCC = local
16361 SDValue SetCC; local
[all...]

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