/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 123 .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
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H A D | SystemZFrameLowering.cpp | 249 MIB.addReg(LowGPR, RegState::Define); 250 MIB.addReg(HighGPR, RegState::Define); 260 MIB.addReg(Reg, RegState::ImplicitDefine);
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H A D | SystemZInstrInfo.cpp | 345 .addReg(SystemZ::CC, RegState::Implicit);;
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.cpp | 67 .addReg(MSP430::FPW, RegState::Kill); 200 .addReg(Reg, RegState::Kill);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 114 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); 134 .addReg(DestReg, RegState::ImplicitDefine); 168 MIB.addReg(DestReg, RegState::Define); 326 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill); 365 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) 423 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
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H A D | MipsSEFrameLowering.cpp | 129 .addReg(VR, RegState::Kill); 176 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill); 178 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); 246 .addReg(VR0, RegState::Kill); 249 .addReg(VR1, RegState::Kill);
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H A D | MipsSEISelDAGToDAG.cpp | 48 unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
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/external/llvm/lib/Target/X86/ |
H A D | X86FrameLowering.cpp | 756 .addReg(FramePtr, RegState::Kill) 892 .addReg(X86::EAX, RegState::Kill) 913 .addReg(StackPtr, RegState::Define | RegState::Implicit) 914 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit) 1142 addReg(JumpTarget.getReg(), RegState::Kill); 1145 addReg(JumpTarget.getReg(), RegState::Kill); 1255 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill) 1535 .addReg(ScratchReg2, RegState [all...] |
H A D | X86FloatingPoint.cpp | 1664 .addReg(X86::ST0, RegState::ImplicitKill) 1665 .addReg(X86::ECX, RegState::ImplicitDefine) 1666 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 1667 .addReg(X86::EDX, RegState::Define | RegState::Implicit) 1668 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
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H A D | X86InstrInfo.cpp | 1825 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit) 1873 .addReg(leaInReg, RegState::Define, X86::sub_16bit) 1883 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0); 1920 .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 1933 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1934 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit); 3699 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 3998 .addReg(Reg, RegState [all...] |
H A D | X86FastISel.cpp | 844 MIB.addReg(RetRegs[i], RegState::Implicit); 1259 .addReg(CReg, RegState::Kill); 1663 // FIXME may need to add RegState::Debug to any registers produced, 2167 MIB.addReg(X86::EBX, RegState::Implicit); 2170 MIB.addReg(X86::AL, RegState::Implicit); 2174 MIB.addReg(RegArgs[i], RegState::Implicit);
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H A D | X86ISelLowering.cpp | 14814 .addReg(X86::RDI, RegState::Implicit) 14815 .addReg(X86::RAX, RegState::ImplicitDefine); 14823 .addReg(X86::EAX, RegState::ImplicitDefine); 14871 .addReg(X86::RAX, RegState::Implicit) 14872 .addReg(X86::RSP, RegState::Implicit) 14873 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 14874 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 14875 .addReg(X86::EFLAGS, RegState [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 226 MIB.addReg(VRBase, RegState::Define); 241 MIB.addReg(VRBase, RegState::Define); 253 MIB.addReg(VRBase, RegState::Define); 684 MIB.addReg(0U, RegState::Debug); 930 MIB.addReg(Reg, RegState::Define | 938 MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.cpp | 104 .addReg(AArch64::XSP, RegState::Define) 646 .addReg(SrcReg, RegState::Kill) 647 .addReg(ScratchReg, RegState::Kill) 672 .addReg(SrcReg, RegState::Kill) 682 .addReg(SrcReg, RegState::Kill)
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb1FrameLowering.cpp | 316 .addReg(ARM::R3, RegState::Define); 322 .addReg(ARM::R3, RegState::Kill);
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H A D | ARMISelLowering.cpp | 6377 .addReg(destlo, RegState::Define) 6378 .addReg(desthi, RegState::Define) 6383 .addReg(GPRPair0, RegState::Define).addReg(ptr)); 6529 .addReg(NewVReg1, RegState::Kill) 6533 .addReg(NewVReg2, RegState::Kill) 6536 .addReg(NewVReg3, RegState::Kill) 6554 .addReg(NewVReg1, RegState::Kill) 6559 .addReg(ARM::CPSR, RegState::Define) 6563 .addReg(ARM::CPSR, RegState::Define) 6564 .addReg(NewVReg2, RegState [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine); 942 .addReg(Base, RegState::Define) 947 .addReg(Base, RegState::Define) 954 .addReg(Base, RegState::Define) 1761 .addReg(EvenReg, RegState::Define) 1762 .addReg(OddReg, RegState::Define)
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/external/llvm/lib/CodeGen/ |
H A D | RegAllocFast.cpp | 93 // RegState - Track the state of a physical register. 94 enum RegState { enum in class:__anon22120::RAFast 113 // PhysRegState - One of the RegState enums, or a virtreg. 177 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState); 248 "Broken RegState mapping"); 278 assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping"); 400 RegState NewState) {
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H A D | PostRASchedulerList.cpp | 457 MIB.addReg(*SubRegs, RegState::ImplicitDefine);
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H A D | IfConversion.cpp | 1004 MIB.addReg(Reg, RegState::Implicit | RegState::Undef);
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H A D | MachineBasicBlock.cpp | 371 .addReg(PhysReg, RegState::Kill);
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H A D | TwoAddressInstructionPass.cpp | 1647 .addReg(DstReg, RegState::Define, SubIdx)
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/external/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.cpp | 288 .addReg(T0, RegState::Implicit) 289 .addReg(T1, RegState::Implicit); 390 .addReg(T0, RegState::Implicit) 391 .addReg(T1, RegState::Implicit); 410 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 424 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 468 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 196 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 1316 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDILCFGStructurizer.cpp | 3157 MachineInstrBuilder(newInstr).addReg(dstReg, RegState::Define); //set target
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