Searched refs:ImplicitDefine (Results 1 - 15 of 15) sorted by relevance
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZElimCompare.cpp | 208 .addReg(SystemZ::CC, RegState::ImplicitDefine);
222 .addReg(SystemZ::CC, RegState::ImplicitDefine);
412 .addReg(SystemZ::CC, RegState::ImplicitDefine);
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| H A D | SystemZFrameLowering.cpp | 260 MIB.addReg(Reg, RegState::ImplicitDefine);
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 40 ImplicitDefine = Implicit | Define, enumerator in enum:llvm::RegState::__anon21841
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
570 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
965 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
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| H A D | Thumb2InstrInfo.cpp | 205 MIB.addReg(DestReg, RegState::ImplicitDefine);
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| H A D | ARMFrameLowering.cpp | 929 .addReg(SupReg, RegState::ImplicitDefine));
944 .addReg(SupReg, RegState::ImplicitDefine));
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| H A D | ARMBaseInstrInfo.cpp | 1000 MIB.addReg(DestReg, RegState::ImplicitDefine);
1033 MIB.addReg(DestReg, RegState::ImplicitDefine);
1054 MIB.addReg(DestReg, RegState::ImplicitDefine);
1074 MIB.addReg(DestReg, RegState::ImplicitDefine);
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| H A D | ARMLoadStoreOptimizer.cpp | 358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);
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| H A D | ARMISelLowering.cpp | 6982 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
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| /external/llvm/lib/CodeGen/ |
| H A D | PostRASchedulerList.cpp | 457 MIB.addReg(*SubRegs, RegState::ImplicitDefine);
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 48 unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
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| H A D | MipsSEInstrInfo.cpp | 134 .addReg(DestReg, RegState::ImplicitDefine);
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| /external/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 1665 .addReg(X86::ECX, RegState::ImplicitDefine)
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| H A D | X86ISelLowering.cpp | 14815 .addReg(X86::RAX, RegState::ImplicitDefine);
14823 .addReg(X86::EAX, RegState::ImplicitDefine);
14935 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
14946 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
14957 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
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| H A D | X86InstrInfo.cpp | 4005 .addReg(Reg, RegState::ImplicitDefine);
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Completed in 283 milliseconds