Searched refs:r1 (Results 1 - 25 of 175) sorted by relevance

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/dalvik/vm/compiler/template/armv5te/
H A DTEMPLATE_SHL_LONG.S9 mov r1, r1, asl r2 @ r1<- r1 << r2
11 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
13 movpl r1, r0, asl ip @ if r2 >= 32, r1<
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H A DTEMPLATE_SHR_LONG.S11 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
13 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
14 mov r1, r1, asr r2 @ r1<- r1 >> r2
H A DTEMPLATE_USHR_LONG.S11 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
13 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
14 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
H A DTEMPLATE_INTERPRET.S9 * r1 - the Dalvik PC to begin interpretation.
19 ldr r1,[lr, #3]
22 ldrne r1,[lr, #3]
25 mov r0, r1 @ set Dalvik PC
H A DTEMPLATE_MUL_LONG.S4 * For JIT: op1 in r0/r1, op2 in r2/r3, return in r0/r1
22 mul ip, r2, r1 @ ip<- ZxW
26 add r1, r2, r10 @ r1<- r10 + low(ZxW + (YxX))
/dalvik/vm/mterp/armv5te/
H A DOP_CONST_4.S3 mov r1, rINST, lsl #16 @ r1<- Bxxx0000
6 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended)
9 SET_VREG(r1, r0) @ fp[A]<- r1
H A DOP_CONST_WIDE_HIGH16.S3 FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended)
6 mov r1, r1, lsl #16 @ r1<- BBBB0000
10 stmia r3, {r0-r1} @ vAA<- r0/r1
H A DOP_RETURN_WIDE.S10 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1
11 stmia r3, {r0-r1} @ retval<- r0/r1
H A DOP_FILL_ARRAY_DATA.S4 FETCH(r1, 2) @ r1<- BBBB (hi)
6 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb
8 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.)
H A DOP_SHL_LONG.S15 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
19 mov r1, r1, asl r2 @ r1<- r1 << r2
21 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r
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H A DOP_SHL_LONG_2ADDR.S13 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
15 mov r1, r1, asl r2 @ r1<- r1 << r2
17 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r
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H A DOP_CONST_WIDE.S4 FETCH(r1, 2) @ r1<- BBBB (low middle)
6 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word)
9 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word)
13 stmia r9, {r0-r1} @ vAA<- r0/r1
H A DOP_GOTO_32.S16 FETCH(r1, 2) @ r1<- AAAA (hi)
17 orr r0, r0, r1, lsl #16 @ r0<- AAAAaaaa
18 adds r1, r0, r0 @ r1<- byte offset
22 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
25 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
H A DOP_MUL_LONG_2ADDR.S12 mov r1, rINST, lsr #12 @ r1<- B
14 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
16 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
17 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1
18 mul ip, r2, r1 @ ip<- ZxW
H A DOP_PACKED_SWITCH.S17 FETCH(r1, 2) @ r1<- BBBB (hi)
19 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
20 GET_VREG(r1, r3) @ r1<- vAA
23 adds r1, r0, r0 @ r1<- byte offset; clear V
27 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
32 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
H A Dbincmp.S12 mov r1, rINST, lsr #12 @ r1<- B
14 GET_VREG(r3, r1) @ r3<- vB
16 FETCH_S(r1, 1) @ r1<- branch offset, in code units
18 mov${revcmp} r1, #2 @ r1<- BYTE branch dist for not-taken
19 adds r2, r1, r1 @ convert to bytes, check sign
H A DOP_MOVE_16.S4 FETCH(r1, 2) @ r1<- BBBB
7 GET_VREG(r2, r1) @ r2<- fp[BBBB]
H A DOP_MOVE_FROM16.S4 FETCH(r1, 1) @ r1<- BBBB
7 GET_VREG(r2, r1) @ r2<- fp[BBBB]
H A DOP_SHR_LONG.S15 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
21 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
23 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
29 mov r1, r1, asr r2 @ r1<- r1 >> r
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H A DOP_SHR_LONG_2ADDR.S13 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
17 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
20 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
21 mov r1, r1, asr r2 @ r1<- r1 >> r
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/dalvik/vm/mterp/armv6t2/
H A DOP_CONST_4.S3 mov r1, rINST, lsl #16 @ r1<- Bxxx0000
6 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended)
8 SET_VREG(r1, r0) @ fp[A]<- r1
H A DOP_IGET_QUICK.S6 FETCH(r1, 1) @ r1<- field byte offset
11 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits)
H A DOP_SHL_LONG_2ADDR.S12 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
14 mov r1, r1, asl r2 @ r1<- r1 << r2
16 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r
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H A DOP_MUL_LONG_2ADDR.S11 mov r1, rINST, lsr #12 @ r1<- B
13 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
15 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
16 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1
17 mul ip, r2, r1 @ ip<- ZxW
H A Dbincmp.S11 mov r1, rINST, lsr #12 @ r1<- B
13 GET_VREG(r3, r1) @ r3<- vB
15 FETCH_S(r1, 1) @ r1<- branch offset, in code units
17 mov${revcmp} r1, #2 @ r1<- BYTE branch dist for not-taken
18 adds r2, r1, r1 @ convert to bytes, check sign

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