| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 188 /// like ADDC/SUBC, which indicate the carry result is always false.
195 ADDC, SUBC, enumerator in enum:llvm::ISD::NodeType
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| H A D | SelectionDAG.h | 943 case ISD::ADDC:
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| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelDAGToDAG.cpp | 256 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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| H A D | MipsSEISelDAGToDAG.cpp | 221 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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| H A D | MipsSEISelLowering.cpp | 169 // ADDENode's second operand must be a flag output of an ADDC node in order
173 if (ADDCNode->getOpcode() != ISD::ADDC)
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | AMDILISelLowering.cpp | 114 setOperationAction(ISD::ADDC, VT, Expand);
214 setOperationAction(ISD::ADDC, MVT::Other, Expand);
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| /external/llvm/lib/Target/R600/ |
| H A D | AMDILISelLowering.cpp | 103 setOperationAction(ISD::ADDC, VT, Expand);
197 setOperationAction(ISD::ADDC, MVT::Other, Expand);
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDILISelLowering.cpp | 114 setOperationAction(ISD::ADDC, VT, Expand);
214 setOperationAction(ISD::ADDC, MVT::Other, Expand);
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| /external/qemu/tcg/ppc/ |
| H A D | tcg-target.c | 347 #define ADDC XO31( 10) macro
1616 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1621 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 196 case ISD::ADDC: return "addc";
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| H A D | LegalizeIntegerTypes.cpp | 1157 case ISD::ADDC:
1291 TLI.isOperationLegalOrCustom(ISD::ADDC,
1296 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2);
1534 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1536 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1541 ISD::ADDC : ISD::SUBC,
1547 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1595 if (N->getOpcode() == ISD::ADDC) {
1596 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
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| H A D | DAGCombiner.cpp | 1110 case ISD::ADDC: return visitADDC(N);
1568 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1608 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
2827 APInt ADDC = ADDI->getAPIntValue(); local
2828 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2837 ADDC |= Mask;
2838 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2841 N0.getOperand(0), DAG.getConstant(ADDC, VT));
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| H A D | SelectionDAG.cpp | 3200 case ISD::ADDC:
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 80 ADDC, // Add with carry enumerator in enum:llvm::ARMISD::NodeType
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| H A D | ARMISelLowering.cpp | 622 setTargetDAGCombine(ISD::ADDC);
667 setOperationAction(ISD::ADDC, MVT::i32, Custom);
995 case ARMISD::ADDC: return "ARMISD::ADDC";
5759 case ISD::ADDC: Opc = ARMISD::ADDC; break;
5901 case ISD::ADDC:
8007 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
8012 // ADDC | hiAdd
8017 assert(AddcNode->getOpcode() == ISD::ADDC
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1394 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1395 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1396 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1397 setOperationAction(ISD::ADDC, MVT::i64, Expand);
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| /external/qemu/tcg/ppc64/ |
| H A D | tcg-target.c | 337 #define ADDC XO31( 10) macro
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| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 207 setOperationAction(ISD::ADDC, MVT::i64, Expand);
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 91 setOperationAction(ISD::ADDC, MVT::i32, Expand);
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 316 case ISD::ADDC:
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| H A D | X86ISelLowering.cpp | 426 setOperationAction(ISD::ADDC, VT, Custom);
12732 case ISD::ADDC: Opc = X86ISD::ADD; break;
12870 case ISD::ADDC:
12936 case ISD::ADDC:
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