| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelDAGToDAG.cpp | 253 case ISD::ADDE: {
256 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
261 if (Opcode == ISD::ADDE) {
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| H A D | MipsSEISelDAGToDAG.cpp | 221 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
336 case ISD::ADDE: {
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| H A D | MipsSEISelLowering.cpp | 114 setTargetDAGCombine(ISD::ADDE);
497 case ISD::ADDE:
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 204 ADDE, SUBE, enumerator in enum:llvm::ISD::NodeType
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| H A D | SelectionDAG.h | 944 case ISD::ADDE: return true;
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | AMDILISelLowering.cpp | 113 setOperationAction(ISD::ADDE, VT, Expand);
213 setOperationAction(ISD::ADDE, MVT::Other, Expand);
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| /external/llvm/lib/Target/R600/ |
| H A D | AMDILISelLowering.cpp | 102 setOperationAction(ISD::ADDE, VT, Expand);
196 setOperationAction(ISD::ADDE, MVT::Other, Expand);
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDILISelLowering.cpp | 113 setOperationAction(ISD::ADDE, VT, Expand);
213 setOperationAction(ISD::ADDE, MVT::Other, Expand);
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| /external/qemu/tcg/ppc/ |
| H A D | tcg-target.c | 346 #define ADDE XO31(138) macro
1617 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1622 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 197 case ISD::ADDE: return "adde";
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| H A D | LegalizeIntegerTypes.cpp | 1160 case ISD::ADDE:
1298 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3);
1534 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1536 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1549 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1598 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
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| H A D | SelectionDAG.cpp | 2026 case ISD::ADDE: {
2044 // With ADDE, a carry bit may be added in, so we can only use this
2048 if (KnownZeroOut >= 2) // ADDE
3201 case ISD::ADDE:
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| H A D | DAGCombiner.cpp | 1112 case ISD::ADDE: return visitADDE(N);
1603 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 81 ADDE, // Add using carry enumerator in enum:llvm::ARMISD::NodeType
|
| H A D | ARMISelLowering.cpp | 668 setOperationAction(ISD::ADDE, MVT::i32, Custom);
996 case ARMISD::ADDE: return "ARMISD::ADDE";
5760 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
5902 case ISD::ADDE:
8007 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
8015 // ADDE
8040 // Look for the glued ADDE.
8045 // Make sure it is really an ADDE
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1386 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1387 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1388 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1389 setOperationAction(ISD::ADDE, MVT::i64, Expand);
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| /external/qemu/tcg/ppc64/ |
| H A D | tcg-target.c | 336 #define ADDE XO31(138) macro
|
| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 208 setOperationAction(ISD::ADDE, MVT::i64, Expand);
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 92 setOperationAction(ISD::ADDE, MVT::i32, Expand);
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 317 case ISD::ADDE:
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| H A D | X86ISelLowering.cpp | 427 setOperationAction(ISD::ADDE, VT, Custom);
12733 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
12871 case ISD::ADDE:
12937 case ISD::ADDE:
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