| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 334 MVT RegVT = local
339 unsigned RegBytes = RegVT.getSizeInBits() / 8;
343 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
356 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
378 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
458 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); local
460 unsigned RegBytes = RegVT.getSizeInBits() / 8;
464 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
474 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
493 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chai
[all...] |
| H A D | LegalizeVectorOps.cpp | 600 EVT RegVT = Value.getValueType(); local
601 EVT RegSclVT = RegVT.getScalarType();
|
| H A D | SelectionDAGBuilder.h | 280 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
286 MVT RegVT; member in struct:llvm::SelectionDAGBuilder::BitTestBlock
|
| H A D | LegalizeIntegerTypes.cpp | 747 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); local
749 // The argument is passed as NumRegs registers of type RegVT.
753 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
769 DAG.getConstant(i * RegVT.getSizeInBits(),
|
| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 454 EVT RegVT = VA.getLocVT(); local
455 switch (RegVT.getSimpleVT().SimpleTy) {
460 << RegVT.getSimpleVT().SimpleTy << "\n";
467 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
473 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
476 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 872 EVT RegVT = VA.getLocVT(); local
873 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
874 RegVT == MVT::i32 || RegVT == MVT::f32) {
878 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
879 } else if (RegVT == MVT::i64) {
883 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
|
| /external/llvm/lib/Target/R600/ |
| H A D | SIISelLowering.cpp | 1066 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT); local
1070 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1081 if (RegVT.isVector())
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1318 EVT RegVT = VA.getLocVT(); local
1319 switch (RegVT.getSimpleVT().SimpleTy) {
1324 << RegVT.getSimpleVT().SimpleTy << "\n";
1331 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 2696 MVT RegVT = VA.getLocVT(); local
2698 const TargetRegisterClass *RC = getRegClassFor(RegVT);
2703 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2715 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue,
2722 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2723 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
2724 (RegVT == MVT::f64 && ValVT == MVT::i64))
2726 else if (Subtarget->isABI_O32() && RegVT == MVT::i32 &&
2730 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3358 MVT RegVT local
3391 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), nullptr, IsSoftFloat); local
3418 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat); local
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 2275 EVT RegVT = VA.getLocVT(); local
2277 if (RegVT == MVT::i32)
2279 else if (Is64Bit && RegVT == MVT::i64)
2281 else if (RegVT == MVT::f32)
2283 else if (RegVT == MVT::f64)
2285 else if (RegVT.is512BitVector())
2287 else if (RegVT.is256BitVector())
2289 else if (RegVT.is128BitVector())
2291 else if (RegVT == MVT::x86mmx)
2293 else if (RegVT
2687 EVT RegVT = VA.getLocVT(); local
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1705 EVT RegVT = VA.getLocVT(); local
1710 if (RegVT == MVT::i32)
1712 else if (RegVT == MVT::i64)
1714 else if (RegVT == MVT::f32)
1716 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
1718 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
1721 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1725 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 2003 EVT RegVT = VA.getLocVT(); local
2017 if (RegVT == MVT::v2f64) {
2987 EVT RegVT = VA.getLocVT(); local
3018 if (RegVT == MVT::f32)
3020 else if (RegVT == MVT::f64)
3022 else if (RegVT == MVT::v2f64)
3024 else if (RegVT == MVT::i32)
3029 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
3033 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3046 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValu
[all...] |