Searched defs:dag (Results 1 - 9 of 9) sorted by relevance
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeTypes.h | 122 explicit DAGTypeLegalizer(SelectionDAG &dag) argument 123 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 130 /// top-down traversal of the dag, legalizing types as it goes. Returns
|
H A D | ScheduleDAGSDNodes.cpp | 55 void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb) { argument 57 DAG = dag; 518 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we 912 return "sunit-dag." + BB->getFullName();
|
H A D | LegalizeDAG.cpp | 216 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) argument 217 : SelectionDAG::DAGUpdateListener(dag), 218 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 219 DAG(dag) { 653 // to phase ordering between legalized code and the dag combiner. This 654 // probably means that we need to integrate dag combiner and legalizer
|
H A D | LegalizeVectorOps.cpp | 129 VectorLegalizer(SelectionDAG& dag) : argument 130 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
|
H A D | SelectionDAGBuilder.h | 539 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo, argument 541 : CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()), 542 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
|
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonMachineScheduler.h | 167 void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) { argument 168 DAG = dag; 210 virtual void initialize(ScheduleDAGMI *dag) override;
|
H A D | HexagonMachineScheduler.cpp | 198 void ConvergingVLIWScheduler::initialize(ScheduleDAGMI *dag) { argument 199 DAG = static_cast<VLIWMachineScheduler*>(dag);
|
/external/llvm/lib/Target/R600/ |
H A D | R600MachineScheduler.cpp | 27 void R600SchedStrategy::initialize(ScheduleDAGMI *dag) { argument 28 assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness"); 29 DAG = static_cast<ScheduleDAGMILive*>(dag);
|
/external/llvm/lib/CodeGen/ |
H A D | MachineScheduler.cpp | 1618 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) { argument 1620 DAG = dag; 2342 void GenericScheduler::initialize(ScheduleDAGMI *dag) { argument 2343 assert(dag->hasVRegLiveness() && 2345 DAG = static_cast<ScheduleDAGMILive*>(dag); 3051 void initialize(ScheduleDAGMI *dag) override { 3052 assert(dag->hasVRegLiveness() && "ILPScheduler needs vreg liveness"); 3053 DAG = static_cast<ScheduleDAGMILive*>(dag);
|
Completed in 1363 milliseconds