/external/valgrind/main/VEX/priv/ |
H A D | host_amd64_defs.h | 175 } Imm; member in union:__anon30778::__anon30779 210 } Imm; member in union:__anon30784::__anon30785
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H A D | host_mips_defs.h | 237 } Imm; member in union:__anon31043::__anon31044
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H A D | host_ppc_defs.h | 249 } Imm; member in union:__anon31099::__anon31100 277 ULong Imm; member in union:__anon31104::__anon31105
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H A D | host_x86_defs.h | 163 } Imm; member in union:__anon31260::__anon31261 197 } Imm; member in union:__anon31266::__anon31267
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILISelDAGToDAG.cpp | 48 inline SDValue getSmallIPtrImm(unsigned Imm); 96 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) { argument 97 return CurDAG->getTargetConstant(Imm, MVT::i32);
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H A D | AMDILISelLowering.cpp | 250 AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const argument
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 245 } Imm; local 248 Imm.f = MO.getFPImm(); 249 Value |= ((uint64_t)Imm.i) << 32;
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/external/llvm/tools/llvm-readobj/ |
H A D | ARMWinEHPrinter.cpp | 238 uint8_t Imm = OC[Offset] & 0x7f; local 242 Imm); 328 uint16_t Imm = ((OC[Offset + 0] & 0x03) << 8) | ((OC[Offset + 1] & 0xff) << 0); local 333 Imm); 417 uint32_t Imm = (OC[Offset + 1] << 8) | (OC[Offset + 2] << 0); local 422 Imm); 430 uint32_t Imm = (OC[Offset + 1] << 16) local 437 static_cast<const char *>(Prologue ? "sub" : "add"), Imm); 445 uint32_t Imm = (OC[Offset + 1] << 8) | (OC[Offset + 2] << 0); local 450 static_cast<const char *>(Prologue ? "sub" : "add"), Imm); 458 uint32_t Imm = (OC[Offset + 1] << 16) local [all...] |
/external/llvm/utils/TableGen/ |
H A D | CodeGenInstruction.h | 307 int64_t Imm; member in struct:llvm::CodeGenInstAlias::ResultOperand 316 ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {} 325 int64_t getImm() const { assert(isImm()); return Imm; }
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H A D | PseudoLoweringEmitter.cpp | 28 enum MapKind { Operand, Imm, Reg }; enumerator in enum:__anon25765::PseudoLoweringEmitter::OpData::MapKind 32 uint64_t Imm; // Integer immedate value. member in union:__anon25765::PseudoLoweringEmitter::OpData::__anon25766 105 OperandMap[BaseIdx + i].Kind = OpData::Imm; 106 OperandMap[BaseIdx + i].Data.Imm = II->getValue(); 234 case OpData::Imm: 236 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
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/external/llvm/lib/Analysis/ |
H A D | TargetTransformInfo.cpp | 95 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const { 96 return PrevTTI->isLegalAddImmediate(Imm); 99 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const { 100 return PrevTTI->isLegalICmpImmediate(Imm); 148 unsigned TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const { argument 149 return PrevTTI->getIntImmCost(Imm, Ty); 153 const APInt &Imm, Type *Ty) const { 154 return PrevTTI->getIntImmCost(Opc, Idx, Imm, Ty); 158 const APInt &Imm, Type *Ty) const { 159 return PrevTTI->getIntImmCost(IID, Idx, Imm, T 152 getIntImmCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const argument 157 getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty) const argument [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 8797 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); local 8799 Imm ^= APInt::getAllOnesValue(BitWidth); 8800 if (Imm == 0 || Imm.isAllOnesValue()) 8802 unsigned ShAmt = Imm.countTrailingZeros(); 8803 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 8821 if ((Imm & Mask) == Imm) { 8822 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
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H A D | FastISel.cpp | 410 uint64_t Imm = CI->getZExtValue(); local 415 isPowerOf2_64(Imm)) { 416 Imm = Log2_64(Imm); 422 isPowerOf2_64(Imm)) { 423 --Imm; 428 Op0IsKill, Imm, VT.getSimpleVT()); 1249 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) { 1261 uint64_t /*Imm*/) { 1276 uint64_t /*Imm*/) { 1284 FastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t Imm, MVT ImmType) argument 1425 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 1497 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 1551 FastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument [all...] |
H A D | SelectionDAG.cpp | 1030 APInt Imm = APInt::getLowBitsSet(BitWidth, local 1033 getConstant(Imm, Op.getValueType()));
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H A D | TargetLowering.cpp | 1450 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); local 1452 DAG.getConstant(Imm, Op0Ty));
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/external/llvm/lib/CodeGen/ |
H A D | StackMaps.cpp | 90 int64_t Imm = (++MOI)->getImm(); local 91 Locs.push_back(Location(StackMaps::Location::Direct, Size, Reg, Imm)); 98 int64_t Imm = (++MOI)->getImm(); local 99 Locs.push_back(Location(StackMaps::Location::Indirect, Size, Reg, Imm)); 105 int64_t Imm = MOI->getImm(); local 106 Locs.push_back(Location(Location::Constant, sizeof(int64_t), 0, Imm));
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/external/llvm/lib/IR/ |
H A D | AutoUpgrade.cpp | 312 unsigned Imm; local 314 Imm = 0; 316 Imm = 1; 318 Imm = 2; 320 Imm = 3; 322 Imm = 4; 324 Imm = 5; 326 Imm = 6; 328 Imm = 7; 334 CI->getArgOperand(1), Builder.getInt8(Imm)); 367 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); local [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64AsmPrinter.cpp | 223 int64_t Imm = MO.getImm(); local 224 O << '#' << Imm; local
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H A D | AArch64ExpandPseudoInsts.cpp | 65 static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) { argument 68 return (Imm >> (ChunkIdx * 16)) & 0xFFFF; 73 static uint64_t replicateChunk(uint64_t Imm, unsigned FromIdx, unsigned ToIdx) { argument 78 const uint64_t Chunk = getChunk(Imm, FromIdx) << ShiftAmt; 80 Imm &= ~(0xFFFFLL << ShiftAmt); 82 return Imm | Chunk; 245 static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) { 250 Imm &= ~(Mask << (Idx * 16)); 253 Imm |= Mask << (Idx * 16); 255 return Imm; [all...] |
H A D | AArch64FastISel.cpp | 208 int Imm; local 211 Imm = AArch64_AM::getFP64Imm(Val); 214 Imm = AArch64_AM::getFP32Imm(Val); 219 .addImm(Imm); 825 uint64_t Imm = CI->getZExtValue(); local 826 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB; 890 uint64_t Imm; local 898 Imm = (isZExt) ? CIVal.getZExtValue() : CIVal.getSExtValue(); 901 Imm = -Imm; 1765 unsigned Imm = 0; local [all...] |
H A D | AArch64ISelDAGToDAG.cpp | 191 /// operand. If so Imm will receive the 32-bit value. 192 static bool isIntImmediate(const SDNode *N, uint64_t &Imm) { argument 194 Imm = C->getZExtValue(); 201 // If so Imm will receive the value. 202 static bool isIntImmediate(SDValue N, uint64_t &Imm) { argument 203 return isIntImmediate(N.getNode(), Imm); 208 // If so Imm will receive the 32 bit value. 210 uint64_t &Imm) { 212 isIntImmediate(N->getOperand(1).getNode(), Imm); 1592 uint64_t Imm local 209 isOpcWithIntImmediate(const SDNode *N, unsigned Opc, uint64_t &Imm) argument 1599 getUsefulBitsFromBitfieldMoveOpd(SDValue Op, APInt &UsefulBits, uint64_t Imm, uint64_t MSB, unsigned Depth) argument 1628 uint64_t Imm = local 1666 uint64_t Imm = local 1908 uint64_t Imm; local [all...] |
H A D | AArch64ISelLowering.cpp | 3784 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { argument 3787 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32)) 3791 return AArch64_AM::getFP64Imm(Imm) != -1; 3793 return AArch64_AM::getFP32Imm(Imm) != -1; 4225 unsigned Imm = VEXTOffsets[i] * getExtFactor(VEXTSrc1); local 4227 DAG.getConstant(Imm, MVT::i32)); 4261 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) { argument 4268 Imm = M[0]; 4273 unsigned ExpectedElt = Imm; 4293 unsigned &Imm) { 4292 isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT, unsigned &Imm) argument 4615 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS); local 4774 unsigned Imm; local 6297 shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const argument [all...] |
H A D | AArch64TargetTransformInfo.cpp | 77 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override; 78 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 80 unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 158 unsigned AArch64TTI::getIntImmCost(const APInt &Imm, Type *Ty) const { argument 166 APInt ImmVal = Imm; 168 ImmVal = Imm.sext((BitSize + 63) & ~0x3fU); 183 const APInt &Imm, Type *Ty) const { 240 unsigned Cost = AArch64TTI::getIntImmCost(Imm, Ty); 244 return AArch64TTI::getIntImmCost(Imm, Ty); 248 const APInt &Imm, Typ 182 getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const argument 247 getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty) const argument [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 240 struct ImmOp Imm; member in union:__anon25114::AArch64Operand::__anon25115 268 Imm = o.Imm; 323 return Imm.Val; 1086 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 1102 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 1515 unsigned Imm = local 1517 Inst.addOperand(MCOperand::CreateImm(Imm)); 1524 unsigned Imm = AArch64_AM::getArithExtendImm(ET, getShiftExtendAmount()); local 1525 Inst.addOperand(MCOperand::CreateImm(Imm)); 1532 unsigned Imm = AArch64_AM::getArithExtendImm(ET, getShiftExtendAmount()); local 2168 const MCExpr *Imm; local 3097 uint64_t Imm = (cast<MCConstantExpr>(SubExprVal))->getValue(); local [all...] |
/external/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 84 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm, 87 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm, 90 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm, 92 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm, 94 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm, 96 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm, 148 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm, 150 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm, 153 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm, 155 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm, 591 DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 600 DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 607 DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 623 DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument 630 DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument 647 DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument 687 DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm, unsigned Add) argument 693 DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm, unsigned Add) argument 699 DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 704 DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 710 DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 715 DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 721 DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 726 DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 732 DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 737 DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 742 DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 747 DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 752 DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 1470 unsigned Imm = fieldFromInstruction(insn, 10, 14); local [all...] |