| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
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21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| 80ada583f3b40ffb201e54cd57c42f9518039c9e |
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07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| 5b00ceaeeabff8c25abb09926343c3fcb06053d8 |
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31-Mar-2012 |
Hal Finkel <hfinkel@anl.gov> |
Fix dynamic linking on PPC64.
Dynamic linking on PPC64 has had problems since we had to move the top-down
hazard-detection logic post-ra. For dynamic linking to work there needs to be
a nop placed after every call. It turns out that it is really hard to guarantee
that nothing will be placed in between the call (bl) and the nop during post-ra
scheduling. Previous attempts at fixing this by placing logic inside the
hazard detector only partially worked.
This is now fixed in a different way: call+nop codegen-only instructions. As far
as CodeGen is concerned the pair is now a single instruction and cannot be split.
This solution works much better than previous attempts.
The scoreboard hazard detector is also renamed to be more generic, there is currently
no cpu-specific logic in it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| 79aa3417eb6f58d668aadfedf075240a41d35a26 |
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17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| 7f370b615515af6422eb0d5d08f1c4c5db95fbbc |
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15-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
Ensure that the nop that should follow a bl call in PPC64 ELF actually does
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| 64c34e253563a8ba6b41fbce2bb020632cf65961 |
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02-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
update PPC 940 hazard rec. to function in postRA mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| c6d08f10bf797cc78068ef30bd0e8812a5bdc9a2 |
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17-Oct-2011 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC 440 scheduler and some associated tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| 2da8bc8a5f7705ac131184cd247f48500da0d74e |
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24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| 6e8f4c404825b79f9b9176483653f1aa927dfbde |
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24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| 2836c283bb1c14baa50994f60769d665da608ad7 |
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16-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Initial hazard recognizer support in post-pass scheduling. This includes
a new toy hazard recognizier heuristic which attempts to direct the
scheduler to avoid clumping large groups of loads or stores too densely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| fc54c552963545a81e4ea38e60460590afb2d5ae |
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15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Generalize the HazardRecognizer interface so that it can be used
to support MachineInstr-based scheduling in addition to
SDNode-based scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| 343f0c046702831a4a6aec951b6a297a23241a55 |
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20-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Experimental post-pass scheduling support. Post-pass scheduling
is currently off by default, and can be enabled with
-disable-post-RA-scheduler=false.
This doesn't have a significant impact on most code yet because it doesn't
yet do anything to address anti-dependencies and it doesn't attempt to
disambiguate memory references. Also, several popular targets
don't have pipeline descriptions yet.
The majority of the changes here are splitting the SelectionDAG-specific
code out of ScheduleDAG, so that ScheduleDAG can be moved to
libLLVMCodeGen.a. The interface between ScheduleDAG-using code and
the rest of the scheduling code is somewhat rough and will evolve.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| 475871a144eb604ddaf37503397ba0941442e5fb |
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27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| 4ee451de366474b9c228b4e5fa573795a715216d |
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29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| 3faad495bc5c23de4852e7a3a13c25203cabfc3e |
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13-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Handle cracked instructions in dispatch group formation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| 88d211f82304e53694ece666d4a2507b170e4582 |
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12-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Several big changes:
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| b0d21ef20c29f4ea46d21b488f17feaa6a8760e1 |
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08-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Change the interface for getting a target HazardRecognizer to be more clean.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| ab5801cb28168b22444a95dd4c3783f4eba25801 |
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07-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
add a couple more load/store instrs, add a newline to the end of file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| 3acbe5d4f0d6163cb761368692c830c1a4f27e31 |
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07-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
This kinda sorta implements "things that have to lead a dispatch group".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
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| c6644188208d4aee9a9d6c428710ec1f69837944 |
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07-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Implement a very very simple hazard recognizer for LSU rejects and ctr set/read
flushes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
|