| 4e35ffa762d763820b7defc14af564b2a02c61c8 |
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03-Oct-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Try again when we've successfully spilled a reg.
Before, we'd spill one reg, then continue on without actually register
allocating, then assertion fail when we tried to use a vgrf number as a
register number.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit d4bcc6591812ebe72a363cf98371de5e5016f481)
This should have been picked when 9237f0e was picked.
Bugzill: https://bugs.freedesktop.org/show_bug.cgi?id=59700
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
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| b22de71c1bc2530e139d75d934e203f4eee89f41 |
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02-Oct-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Implement register spilling.
To validate this code, I ran piglit -t vs quick.tests with the "go spill
everything" debugging code enabled. There was only one regression:
glsl-vs-unroll-explosion simply ran out of registers. This should be
fine in the real world, since no one actually spills every single
register.
NOTE: This is a candidate for the 9.0 branch. Even if it proves to have
bugs, it's likely better than simply failing to compile.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 9237f0ea8d176fb5dcd41868dcc723fe34f6b1f3)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
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| 1e188f2daef1ae31224d2429bcc1fab75c81fb36 |
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10-May-2012 |
Eric Anholt <eric@anholt.net> |
intel: Fix signed/unsigned comparison warnings.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
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| 9195191e50429d9cf25e6498f9fb108758ac2be6 |
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27-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Avoid allocating registers in to the gen7 MRF hack region.
This is the corresponding fix to the previous one for the FS, but I
don't have a particular test for it.
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
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| b972744c78e45928876ea781b9eeef09b3baf083 |
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12-Jan-2012 |
Eric Anholt <eric@anholt.net> |
mesa: Make the register allocator allocation take a ralloc context.
This fixes a memory leak on i965 context destruction.
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
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| 14081695137c095f0a8430779ecb09165bec6455 |
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07-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: When failing due to lack of spilling, don't continue on.
Fixes assertion failure from double-free in oglc
glsl-arrayobject constructor.declaration.structure
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
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| 8adcad213ef6cbbaa9adf1485827125cc05aa033 |
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31-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix GPU hangs in shaders with large virtual GRFs pre-gen6.
If you get your total GRF count wrong, you write over some other
shader's g0, and the GPU fails shortly thereafter.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
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| 2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f |
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26-Aug-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Fix Android build by removing relative includes
Replace each occurence of
#include "../glsl/*.h"
with
#include "glsl/*.h"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
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| f4db75547f38f08665efac3daf1599fdc5594bb7 |
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17-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Implement proper register allocation instead of 1:1 mapping.
Fixes vs-atan-* and several others. This is not the real solution we
eventually want, which will pack floats, vec2s, and vec3s into vec4
registers, but this code should provide the framework for that.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
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| eb5454f20a7ad998f2789d9b2a91adcd41c887b6 |
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16-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Remove stale comment about compressed instructions.
This was copy'n'paste from the fragment shader, and didn't make sense
here.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
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| e8980c61b2932cd4c8791fcc5afdb54fa033c224 |
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11-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix the trivial register allocator's failure path.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
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| 7b91eefe7cbe771397684b5970f7c04313baa2f0 |
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09-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Slightly improve the trivial reg allocator to skip unused regs.
This fixes most of the regressions in the vs array test set from the
varying array indexing work, since the giant array that was originally
allocated in virtual GRF space never gets used and is only ever
read/stored from scratch space.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
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| af3c9803d818fd33139f1247a387d64b967b8992 |
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02-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Start adding the VS visitor and codegen.
The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's
currently controlled by the INTEL_NEW_VS=1 environment variable, and
only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
|