| 68da5dfc2c2e9c0aca47431076be0cd43406d4aa |
|
30-Aug-2012 |
Paul Berry <stereotype441@gmail.com> |
intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.
This patch modifies intel_region_get_aligned_offset() to make the
appropriate calculation when the blorp engine sets up a W-tiled
stencil buffer using a Y-tiled SURFACE_STATE.
Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit b760c9913dcff848a2aa0e60abeb48e596ae8fee)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 96fd94ba9421c7c3072988f999ee869534f2bc2a |
|
30-Aug-2012 |
Paul Berry <stereotype441@gmail.com> |
intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.
When the blorp engine is performing a blit from one stencil buffer to
another, it sets up the surface state for these buffers as Y-tiled, so
it needs to be able to force intel_region_get_tile_masks() to return
the appropriate masks for a Y-tiled region.
Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 50dec7fc2d5ba813aaa822596d124098a22db301)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 0e723b135bfd59868c92c3ae243f1adaedaec3a5 |
|
12-Jul-2012 |
Eric Anholt <eric@anholt.net> |
intel: Add performance debug for some common GPU stalls.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 3ec0e55b63db3c1067f3bbf4563beb3b98a19288 |
|
15-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Fix mipmap offsets for HiZ and separate stencil buffers.
When rendering to a miplevel other than 0 within a color, depth,
stencil, or HiZ buffer, we need to tell the GPU to render to an offset
within the buffer, so that the data is written into the correct
miplevel. We do this using a coarse offset (in pages), and a fine
adjustment (the so-called "tile_x" and "tile_y" values, which are
measured in pixels).
We have always computed the coarse offset and fine adjustment using
intel_renderbuffer_tile_offsets() function. This worked fine for
color and combined depth/stencil buffers, but failed to work properly
when HiZ and separate stencil were in use. It failed to work because
there is only one set of fine adjustment controls shared by the HiZ,
depth, and stencil buffers, so we need to choose tile_x and tile_y
values that are compatible with the tiling of all three buffers, and
then compute separate coarse offsets for each buffer.
This patch fixes the HiZ and separate stencil case by replacing the
call to intel_renderbuffer_tile_offsets() with calls to two functions:
intel_region_get_tile_masks(), which determines how much of the
adjustment can be performed using offsets and how much can be
performed using tile_x and tile_y, and
intel_region_get_aligned_offset(), which computes the coarse offset.
intel_region_get_tile_offsets() is still used for color renderbuffers,
so to avoid code duplication, I've re-worked it to use
intel_region_get_tile_masks() and intel_region_get_aligned_offset().
On i965 Gen6, fixes piglit tests
"texturing/depthstencil-render-miplevels 1024 X" where X is one of
(depth, depth_and_stencil, depth_stencil_single_binding, depth_x,
depth_x_and_stencil, stencil, stencil_and_depth, stencil_and_depth_x).
On i965 Gen7, the variants of
"texturing/depthstencil-render-miplevels" that contain a stencil
buffer still fail, due to another problem: Gen7 seems to ignore the 3
LSB's of the tile_y adjustment (and possibly also tile_x).
v2: Removed spurious comments. Added assertions to check
preconditions of intel_region_get_aligned_offset().
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 9cb777eb71dde895ca0ad3454a9b44252e9b402e |
|
27-Mar-2012 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
intel: fix un-blanced map_refcount issue
This is a regression introduced by commit cdcfd5, which forget to
increase the map_refcount for successfully-mapped region. Thus caused a
wrong non-blanced map_refcount.
This would fix the regression found in the two following webglc testcase
on Pineview platform:
texture-npot.html
gl-max-texture-dimensions.html
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| cdcfd5d1d60179e60e3a0a47dda71bfe91083105 |
|
27-Feb-2012 |
Anuj Phogat <anuj.phogat@gmail.com> |
intel: Fix a case when mapping large texture fails
This patch handles a case when mapping a large texture fails
in drm_intel_gem_bo_map_gtt(). These changes avoid assertion
failure later in the driver as reported in following bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=44970
https://bugs.freedesktop.org/show_bug.cgi?id=46303
Testing: No regressions in piglit quick.tests
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 4cb1d6a25e4749ec5e0389ca3da468adbbe5299e |
|
30-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Make intel_region_map return void *.
We don't gripe about void * arithmetic for our driver, and this
prevents silly casting when assigning the result of mapping to
non-byte types.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| f8377b411dfe3c879eaab11bb86f509178796bd1 |
|
22-Sep-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Add 'mode' param to intel_region_map
The 'mode' param is a bitset of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT.
A future commit will perform buffer resolves in intel_region_map(). So,
even though the access mode is irrelevant to the GTT, the extra
information allows us to intelligently avoid unneccessary buffer resolves.
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| e9adfa2ba1af9c3579b25327335c47118b6c7c3f |
|
06-Oct-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Assert that no batch is emitted if a region is mapped
What I would prefer to assert is that, for each region that is currently
mapped, no batch is emitted that uses that region's bo. However, it's much
easier to implement this big hammer.
Observe that this requires that the batch flush in intel_region_map() be
moved to within the map_refcount guard.
v2: Add comments (borrowed from anholt's reply) explaining why the
assertion is a good idea.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| b07c78bfe94c17e6fccba70923b03a29c751fde1 |
|
29-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Consolidate texture validation copy code, and reuse it correctly.
The path for ->Data was failing to be called for the FBO draw offset
fallback, and also had mismatched compressed texture support code.
This drops the intel_prepare_render() in the blit path. We aren't
copying to/from a GL_FRONT buffer, so it doesn't matter.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 8004a1cb95b8a195f3f4bbaa8d39d2f3297167de |
|
22-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Rename region->buffer to region->bo, and remove accessor function.
We call all the other drm_intel_bo pointers in intel/*.h "bo", so this
one was rather out of place.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| bc0335fc0e0bd6a777ef16ad5245d35ccf7adcf6 |
|
21-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Remove the pbo zero-copy code.
There were notes about the possibility of slowdowns due to zcopy from
a PBO due to thrashing around of the region. Slowdowns are even more
likely now that textures are generally tiled, which a zcopy wouldn't
get. Additionally, there were no checks on the buffer size to ensure
that the hardware-required rounding was present, which could result in
GPU hangs on large zcopy PBOs.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| d8f65c07e9f3a5948c8bee95482bcab651b33c01 |
|
08-Jul-2011 |
Brian Paul <brianp@vmware.com> |
intel: add null src pointer check in intel_region_reference()
Fixes segfault when running cubemap demo on i945. This happened
when intel_region_reference() was called in i915_set_draw_region()
with depth_region=NULL.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 036b74a7f8adc745c7af089129f070b8e5b8f4bd |
|
29-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Allow intel_region_reference() with *dst != NULL.
This should help us avoid leaking regions in region reference code by
making the API more predictable.
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| b17aab5753a6d14c9e757bedb186963b2dae8823 |
|
31-May-2011 |
Eric Anholt <eric@anholt.net> |
intel: Move the draw_x/draw_y to the renderbuffer where it belongs.
It was originally located in the region because the tracking of
depth/color buffers was on the regions, and getting back to the irb
would have been tricky. Now, we're keying off of the renderbuffer in
more places, which means we can move these fields where they belong.
This could fix potential rendering failure with a single texture
having multiple images attached to different renderbuffers across
shareCtx (as far as I can tell, this was the only failure we could
cause, since anything else should trigger intel_render_texture in
between, for example a BindFramebuffer).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 3e43adef95ee24dd218279d2de56939b90edcb4c |
|
13-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for rendering to depthbuffer mipmap levels > 0.
Fixes
GL_ARB_depth_texture/fbo-clear-formats
GL_EXT_packed_depth_stencil/fbo-clear-formats
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| f627d429bda8196fd20f2023374ad6d34e4becb6 |
|
04-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: Add some defense against bo allocation failure
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 8d68a90e225d831a395ba788e425cb717eec1f9a |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: use pwrite for batch
It's faster. Not only is the memcpy more efficiently performed in the
kernel (making up for the system call overhead), but by not using mmap
we remove the greater overhead of tracking the vma of every batch.
And it means we can read back from the batch buffer without incurring
the cost of a uncached read through the GTT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| f301932dba4cc75e810e0c051e39247128a899fc |
|
07-Jun-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Support EGL_MESA_image_drm
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 9087ba128089ed0dc00e6eb38f37126fb7557d3b |
|
04-Jun-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Take an intel_screen pointer in intel_alloc_region_* functions
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 85cfe321805264686ef8989e45a911a999ed928a |
|
05-Aug-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: Check for region allocation failure.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 34474fa4119378ef9fbb9fb557cc19c0a1ca1f7e |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.
The slightly less mechanical change of converting the emit_reloc calls
will follow.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| c4775a27e3aaa2006b98f225387499b79bc609ef |
|
10-May-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop intelFlush()
Now that intel_flush() deosn't use the needs_mi_flush argument, we can
finally drop one of the two flush functions.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| e1e48ea15c1fe448f0b69e086b66c1123dc98bb7 |
|
17-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Respect src pitch in _mesa_copy_rect().
If a non-zero src_y was used, this would break piglit
depth-level-clamp.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| da011faf48155a5c02ebc1fe1fa20a4f54b8c657 |
|
17-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Rely on allocated region pitch for the miptree pitch.
Bug #26966: 945 miptree pitch disagreement with libdrm.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 32f143b4327521a058dc05f0ab9087a5696b9618 |
|
17-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove extra tiling setting after allocating a tiled region.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| a589da14dee0c2a32e6e529f1a390b01a3ee4001 |
|
16-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix inversion for glCopyPixels to/from FBOs.
fixes piglit fbo-copypix.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| bb35000b4b6dfe60048b2f5d60bc102c4a7fd791 |
|
05-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove non-kernel-exec-fencing support.
Shaves 60k off the driver from removing the broken spans code. This
means we now require 2.6.29, which seems fair given that it's a year
old and we've removed support for non-KMS already in the last release
of 2D.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 179d2c0e0bcf96fc40107882ccab909af8c89853 |
|
03-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Use drm_intel_bo_alloc_tiled for region allocs.
This moves the logic for how to align pitches, heights, and sizes of
objects to one central location. Fixes rendering with texture tiling
on i915. Note that current libdrm is required for the change for
I915_TILING_NONE pitch alignment.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 0aa610571162eafc8c31c3d26c3676b6aead82df |
|
18-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Include main/hash.h using "" instead of <>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| d449627829e1a4a3250a1a723af2f4e3cd5fd194 |
|
18-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Implement the DRI2 invalidate function properly
This uses a stamp mechanisms to mark the DRI drawable as invalid.
Instead of immediately updating the buffers we just bump the drawable
stamp and call out to DRI2GetBuffers "later".
"Later" used to be at LOCK_HARDWARE time, and this patch brings back
callouts at the points where we used to call LOCK_HARDWARE. A new function,
intel_prepare_render(), is called where we used to call LOCK_HARDWARE,
and if the buffers are invalid, we call out to DRI2GetBuffers there.
This lets us invalidate buffers only when notified instead of on
every glViewport() call. If the loader calls the DRI invalidate
entrypoint, we disable viewport triggered buffer invalidation.
Additionally, we can clean up the old viewport mechanism a bit,
since we can just invalidate the buffers and not worry about
reentrancy and whatnot.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 2d99588b3556928a0879b4160210ac771dbf1f0b |
|
11-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Track named regions and make sure we only have one region per named bo
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| fa43956b5ce6b48d29f973fc54bd77d1a11e32e4 |
|
11-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
i915: Remove left-over drmUnmap()
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| f20e83210e81a33712f52eaa8d944d116b56b46c |
|
28-Jan-2010 |
Eric Anholt <eric@anholt.net> |
intel: Set the region's tiling to none when attaching a PBO to a region.
Note that when detaching the PBO from the region and making a new BO
for the region, we don't make it tiled even if the region originally
was.
Fixes piglit pbo-teximage-tiling.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 9b22427911ad27efc1f36faee9462c6082d0417c |
|
25-Jan-2010 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
src/mesa/drivers/dri/intel/intel_screen.c
src/mesa/drivers/dri/intel/intel_swapbuffers.c
src/mesa/drivers/dri/r300/r300_emit.c
src/mesa/drivers/dri/r300/r300_ioctl.c
src/mesa/drivers/dri/r300/r300_tex.c
src/mesa/drivers/dri/r300/r300_texstate.c
|
| fb6bff3712d71cfe131fbf70154d326cdf39e7c8 |
|
23-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
intel: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| f55d0920cd8e504a09e3741716fc47381c03f6ac |
|
02-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop DRI1 static regions
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 01dc463e5d5513e059eea601710cd4babe02610d |
|
02-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop LOCK/UNLOCK_HARDWARE()
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 827ba44f6ee83ab21c6a2b09323f6f1df4a7d4c8 |
|
18-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove non-GEM support.
This really isn't supported at this point. GEM's been in the kernel for
a year, and the fake bufmgr never really worked.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| caf3038123d6d29afd7d1f0cd6db98a2282c3ca1 |
|
26-Oct-2009 |
Eric Anholt <eric@anholt.net> |
Make a convenient int for what chipset generation we're on.
gen2/3/4 are easier to say than "8xx, 915-945/g33/pineview, 965/g45/misc",
and compares on generation are often easier than stringing together a bunch
of chipset checks.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 0c309bb494b6ee1c403442d1207743f749f95b6e |
|
09-Sep-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_5_branch' into mesa_7_6_branch
Conflicts:
Makefile
configs/default
progs/glsl/Makefile
src/gallium/auxiliary/util/u_simple_shaders.c
src/gallium/state_trackers/glx/xlib/xm_api.c
src/mesa/drivers/dri/i965/brw_draw_upload.c
src/mesa/drivers/dri/i965/brw_vs_emit.c
src/mesa/drivers/dri/intel/intel_context.h
src/mesa/drivers/dri/intel/intel_pixel.c
src/mesa/drivers/dri/intel/intel_pixel_read.c
src/mesa/main/texenvprogram.c
src/mesa/main/version.h
|
| 945d34e88ab7413299227fea56acc746010bb2e9 |
|
08-Aug-2009 |
Eric Anholt <eric@anholt.net> |
intel: Align untiled region height to 2 according to 965 docs.
This may or may not be required pre-965, but it doesn't seem unlikely, and
I'd rather be safe.
(cherry picked from commit b053474378633249be0e9f24010650ffb816229a)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| b053474378633249be0e9f24010650ffb816229a |
|
13-Aug-2009 |
Eric Anholt <eric@anholt.net> |
intel: Align untiled region height to 2 according to 965 docs.
This may or may not be required pre-965, but it doesn't seem unlikely, and
I'd rather be safe.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| ceb8afcca5b0a52b005a782ea54b301beaee1a15 |
|
08-Aug-2009 |
Eric Anholt <eric@anholt.net> |
intel: Align region height as required for tiled regions.
Otherwise, we would address beyond the end of our buffers. Fixes reliable
GPU segfault with texture_tiling=true and oglconform shadow.c.
Bug #22406.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 6e0be1cc343bc8eee5069d7f2f53b12b1a29c216 |
|
06-Aug-2009 |
Brian Paul <brianp@vmware.com> |
intel: move blit call out of assert()
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| ae1bfb6427cc10a851c80e020cbdc210fe238d85 |
|
03-Jul-2009 |
Eric Anholt <eric@anholt.net> |
intel: Flush when mapping buffer objects so writes don't get reordered.
While GEM covers this for execution it knows about, it doesn't know about
the batchbuffer we're preparing. Fixes piglit vbo-map-remap.c testcase.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 3927874d9c7fafb61651d0fc69547c8e010181f5 |
|
29-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Make LOCK_HARDWARE recursive to avoid hand-rolling recursiveness.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 8f81a6468fdbc7320800ea497791e3e1b8f782ca |
|
22-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Avoid trying to do blits to Y tiled regions.
This is somewhat nasty, but we need to do Y-tiled depth for FBO support.
May help with corruption and hangs since enabling texture tiling, and
since switching depth textures to Y tiled.
Fixes piglit depthtex.c on 965.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 246d59c29e3e5a57dcf2f60ad429eb1606193ef0 |
|
22-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Fix some potential writes to zero-copy PBOs when used as regions.
I was in the midst of fixing some blitting-with-Y-tiled issues when I
noticed this. Hopefully PBO usage will be a little more robust, as a
result.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 6a49473ab5797b1e6ce021e396902f9cb77674ef |
|
22-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove long-unused intel_region_fill and intelEmitFillBlit.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 3b08a43f32d04a0522596d3d37b1c1874e04d5c3 |
|
20-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Don't map regions with drm_intel_gem_bo_map_gtt() unless they're tiled.
This fixes a regression in region read performance that came in with the
texture tiling changes. Ideally we'd have an access flag coming in so we
could also use bo_map_gtt for writing, like we do for buffer objects.
Bug #22190
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| cca30245bd6a5a713f0dc3278c37d9bd1f726e72 |
|
18-Jun-2009 |
Chia-I Wu <olvaffe@gmail.com> |
intel: Do not access pbo's buffer directly when attaching.
pbo might be system buffer based or attached to another region. Call
intel_bufferobj_buffer to make sure pbo has a buffer of its own.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| ed91389618d05a3f660b34e0bac4be08134af6b7 |
|
18-Jun-2009 |
Chia-I Wu <olvaffe@gmail.com> |
intel: Data are copied in the wrong direction when breaking COW tie.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| bd10f0e84f1491363d76d92dcbd410ab5cc43dbe |
|
12-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix tiling for FBO depth attachments by making DEPTH_COMPONENT Y tiled.
This may hurt if miptree relayout occurs, since we can't blit Y tiled
objects. But it corrects depth tests on FBOs using textures.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 2d57e9640819c7889304d1de9dd5500a1a0f66de |
|
05-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Fix intel_region_unmap to do unmap, not map.
Thanks to Shuang He for catching this.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 1ba96651e12b3c74fb9c8f5a61b183ef36a27b1e |
|
03-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add support for tiled textures.
This is about a 30% performance win in OA with high settings on my GM45,
and experiments with 915GM indicate that it'll be around a 20% win there.
Currently, 915-class hardware is seriously hurt by the fact that we use
fence regs to control the tiling even for 3D instructions that could live
without them, so we spend a bunch of time waiting on previous rendering in
order to pull fences off. Thus, the texture_tiling driconf option defaults
off there for now.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 1d112207716774b32c0cc846304c2c50bf40e812 |
|
08-May-2009 |
Robert Ellison <papillo@vmware.com> |
i965: improve debug logging
Looking for memory leaks that were causing crashes in my environment
in a situation where valgrind would not work, I ended up improving
the i965 debug traces so I could better see where the memory was
being allocated and where it was going, in the regions and miptrees
code, and in the state caches. These traces were specific enough
that external scripts could determine what elements were not being
released, and where the memory leaks were.
I also ended up creating my own backtrace code in intel_regions.c,
to determine exactly where regions were being allocated and for what,
since valgrind wasn't working. Because it was useful, I left it in,
but disabled and compiled out. It can be activated by changing a flag
at the top of the file.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| ecdf3ce436c004365c4d3c468bf1f9ef9138853e |
|
26-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: add missing init for region->width
This doesn't seem to really effect anything but seeing width=0 in drawing
regions was confusing.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 40dd024be618d805b3744e15d25e115018641324 |
|
18-Feb-2009 |
Eric Anholt <eric@anholt.net> |
intel: tell libdrm whether we want a cpu-ready or gpu-ready BO for regions.
This lets us avoid allocing new buffers for renderbuffers, finalized miptrees,
and PBO-uploaded textures when there's an unreferenced but still active one
cached, while also avoiding CPU waits for batchbuffers and CPU-uploaded
textures. The size of BOs allocated for a desktop running current GL
cairogears on i915 is cut in half with this.
Note that this means we require libdrm 2.4.5.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 7f0b6a779601d00ab86f794e174d0b4c0ba08c42 |
|
30-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: more debug info
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| b359350017a8f0328912f19d233bcdcc256aded1 |
|
20-Dec-2008 |
Dave Airlie <airlied@redhat.com> |
Remove third buffer support from Mesa.
This is part of the deprecated pageflipping infrastructure.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| dd17cd600a25ad916185eaeec968563adbab76f9 |
|
14-Oct-2008 |
Eric Anholt <eric@anholt.net> |
intel: Use dri_bo_get_tiling to get tiling mode of buffers we get from names.
Previously, we were trying to pass a name to the GEM GET_TILING_IOCTL,
which needs a handle, and failing. None of our buffers were tiled yet, but
they will be at some point with DRI2 and UXA.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 7d99ddcb2bb09f1f54d91e6e20e42d217a5bccdf |
|
26-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: Fix a number of memory leaks on context destroy.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 8db761409dadc2e899d4e7107eff3aa07b07aa11 |
|
13-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: Add a width field to regions, and use it for making miptrees in TFP.
Otherwise, we would use the pitch as width of the texture, and compiz would
render the pitch padding on the right hand side.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 3628185f566e178a12b493fb89abf52b4b281f99 |
|
06-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| f56b569e9af356c11869ee49a4669bb01b75397e |
|
13-Aug-2008 |
Kristian Høgsberg <krh@redhat.com> |
DRI2: Drop sarea, implement swap buffers in the X server.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 2e79b491fc45d6f608c042e007fa477d9ab44586 |
|
14-Aug-2008 |
Dave Airlie <airlied@redhat.com> |
intel: remove unneeded mem type and args
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 2e841880cfc1006a2818d4a8bfefd21136dc39a9 |
|
11-Jul-2008 |
Eric Anholt <eric@anholt.net> |
drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| f059a3302260075e9cfd35649dc3877726291d8d |
|
27-Jun-2008 |
Eric Anholt <eric@anholt.net> |
intel: Fix locking when doing intel_region_cow().
This was broken in the merge of 965 blit support. It tried to lock only
when things were already locked.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 93f701bc3619864ac6f067d37212e96545a57e16 |
|
26-Jun-2008 |
Eric Anholt <eric@anholt.net> |
intel: Replace sprinkled intel_batchbuffer_flush with MI_FLUSH or nothing.
Most of these were to ensure that caches got synchronized between 2d (or meta)
rendering and later use of the target as a source, such as for texture
miptree setup. Those are replaced with intel_batchbuffer_emit_mi_flush(),
which just drops an MI_FLUSH. Most of the remainder were to ensure that
REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped.
Those are now replaced by automatically flushing those when dropping the lock.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 4b5b008d54e86ac4f0a2176429d062100978ca8c |
|
03-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert drivers to using libdrm bufmgr code.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| eb10cdc838fc31ea2cf59f556f6f7d8b072f5bae |
|
02-May-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Fix build for GEM. TTM is now disabled, and fencing is gone.
Fencing was used in two places: ensuring that we didn't get too many frames
ahead of ourselves, and glFinish. glFinish will be satisfied by waiting on
buffers like we would do for CPU access on them. The "don't get too far ahead"
is now the responsibility of the execution manager (kernel).
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| c5c73c1b605611faf0f06df9b5d08d8984388238 |
|
21-Jan-2008 |
Kristian Høgsberg <krh@temari.boston.redhat.com> |
Hook up i915 driver to new DRI2 infrastructure.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| c0e026c8090954ddb629a01cc1a93c61b2fc8298 |
|
05-Feb-2008 |
Eric Anholt <eric@anholt.net> |
[965] Bug 14314: assertion failure with with !AIGLX and depth=24 visual.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| fd776e10b327b6a49b76c5082e4cc48059c6ad2e |
|
05-Feb-2008 |
Eric Anholt <eric@anholt.net> |
Replace usage of DRM_BO_FLAG_MEM_TT in intel_regions.c with local/cached.
In addition to potentially binding when it was about to be mapped anyway,
failure to use CACHED_MAPPED means eating a full wbinvd on validate. Thanks to
airlied for catching this.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| a9a483b43ec090408148d069bc184c0a21323654 |
|
01-Feb-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[intel] use _mesa_copy_rect for upload compressed texture,
this fix bad texture issue in some games(UT and quake).
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 46eb02b60920a920b782bacb15f01b44e18f888d |
|
22-Jan-2008 |
Kristian Høgsberg <krh@temari.boston.redhat.com> |
[intel] Clean up references to screen buffer metrics.
The screen wide info such as pitch and cpp are obsoleted by the FBO
changes, so clean up the last few references to those, except for
setting up the legacy screen regions.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 3fe9d5cbb7c680c6fb88a2eba678b28a2a06949e |
|
15-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Merge intel_buffer_objects to shared.
965 gains fixed TTM typing of the buffer object buffers and unused PBO
functions, and 915 gains buffer size == 0 fixes from 965.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| f5b3cd46202517c21fcfcec0102732411df1af18 |
|
15-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Use shared intel_regions.c.
This adds (so far) unused PBO functions, and holding the lock while writing
to regions (which may be shared static screen regions).
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| c5456a6b24525e9307e58fc2a02a6f62ca507730 |
|
14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Remove useless intel_region_idle.
The idling it was trying to ensure was covered by the
intel_miptree_image_map()->intel_region_map() that immediately followed it.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 7c71ef3a3d0cf2620525f468960cdc76a0fb0d33 |
|
12-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Move bufmgr back to context instead of screen, fixing glthreads.
Putting the bufmgr in the screen is not thread-safe since the emit_reloc
changes. It also led to a significant performance hit from pthread usage
for the attempted thread-safety (up to 12% of a cpu spent on refcounting
protection in single-threaded 965). The motivation had been to allow
multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| f00a64999c197e6a96e65fd00f64224a6f22c9fa |
|
17-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Add 965 support to shared intel_blit.c
This requires that regions grow a marker of whether they are tiled or not,
because fence (surface) registers are ignored by the 965 2D engine.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 9b461d4d029497dd6f71e60220849e1b66bb8cf5 |
|
17-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[i915] Pass static region names in so debugging says more than "static region".
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|
| 77a5bcaff43df8d54e0e0ef833726e4b41d7eb36 |
|
07-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Move over files that will be shared with 965-fbo work.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_regions.c
|