Lines Matching defs:SU
186 /// IsReachable - Checks if SU is reachable from TargetSU.
187 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
188 return Topo.IsReachable(SU, TargetSU);
191 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
193 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
194 return Topo.WillCreateCycle(SU, TargetSU);
197 /// AddPred - adds a predecessor edge to SUnit SU.
200 void AddPred(SUnit *SU, const SDep &D) {
201 Topo.AddPred(SU, D.getSUnit());
202 SU->addPred(D);
205 /// RemovePred - removes a predecessor edge from SUnit SU.
208 void RemovePred(SUnit *SU, const SDep &D) {
209 Topo.RemovePred(SU, D.getSUnit());
210 SU->removePred(D);
214 bool isReady(SUnit *SU) {
216 AvailableQueue->isReady(SU);
219 void ReleasePred(SUnit *SU, const SDep *PredEdge);
220 void ReleasePredecessors(SUnit *SU);
223 void AdvancePastStalls(SUnit *SU);
224 void EmitNode(SUnit *SU);
366 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
382 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());
510 /// Always update LiveRegDefs for a register dependence even if the current SU
526 void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) {
528 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
530 ReleasePred(SU, &*I);
537 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) &&
542 LiveRegGens[I->getReg()] = SU;
552 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode())
560 CallSeqEndForStart[Def] = SU;
564 LiveRegGens[CallResource] = SU;
623 void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) {
632 // if (!SU->getNode() || !SU->getNode()->isMachineOpcode()) return;
634 unsigned ReadyCycle = SU->getHeight();
645 if (SU->isCall)
653 HazardRec->getHazardType(SU, -Stalls);
665 void ScheduleDAGRRList::EmitNode(SUnit *SU) {
670 if (!SU->getNode())
673 switch (SU->getNode()->getOpcode()) {
675 assert(SU->getNode()->isMachineOpcode() &&
693 if (SU->isCall) {
699 HazardRec->EmitInstruction(SU);
702 static void resetVRegCycle(SUnit *SU);
707 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) {
709 DEBUG(SU->dump(this));
712 if (CurCycle < SU->getHeight())
713 DEBUG(dbgs() << " Height [" << SU->getHeight()
721 SU->setHeightToAtLeast(CurCycle);
724 EmitNode(SU);
726 Sequence.push_back(SU);
728 AvailableQueue->scheduledNode(SU);
738 ReleasePredecessors(SU);
741 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
743 // LiveRegDegs[I->getReg()] != SU when SU is a two-address node.
744 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] == SU) {
755 if (LiveRegDefs[CallResource] == SU)
756 for (const SDNode *SUNode = SU->getNode(); SUNode;
768 resetVRegCycle(SU);
770 SU->isScheduled = true;
781 if (SU->getNode() && SU->getNode()->isMachineOpcode())
789 /// CapturePred - This does the opposite of ReleasePred. Since SU is being
806 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
807 DEBUG(dbgs() << "*** Unscheduling [" << SU->getHeight() << "]: ");
808 DEBUG(SU->dump(this));
810 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
813 if (I->isAssignedRegDep() && SU == LiveRegGens[I->getReg()]){
827 for (const SDNode *SUNode = SU->getNode(); SUNode;
832 LiveRegDefs[CallResource] = SU;
833 LiveRegGens[CallResource] = CallSeqEndForStart[SU];
839 if (LiveRegGens[CallResource] == SU)
840 for (const SDNode *SUNode = SU->getNode(); SUNode;
852 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
859 LiveRegDefs[I->getReg()] = SU;
865 if (SU->getHeight() < MinAvailableCycle)
866 MinAvailableCycle = SU->getHeight();
868 SU->setHeightDirty();
869 SU->isScheduled = false;
870 SU->isAvailable = true;
873 SU->isPending = true;
874 PendingQueue.push_back(SU);
877 AvailableQueue->push(SU);
879 AvailableQueue->unscheduledNode(SU);
895 SUnit *SU = *I;
896 for (; SU->getHeight() > HazardCycle; ++HazardCycle) {
899 EmitNode(SU);
905 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) {
918 assert(!SU->isSucc(OldSU) && "Something is wrong!");
927 static bool isOperandOf(const SUnit *SU, SDNode *N) {
928 for (const SDNode *SUNode = SU->getNode(); SUNode;
938 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
939 SDNode *N = SU->getNode();
943 if (SU->getNode()->getGluedNode())
972 DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n");
978 unsigned OldNumVals = SU->getNode()->getNumValues();
980 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i));
981 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals-1),
1017 // Record all the edges to and from the old SU, by category.
1023 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1032 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1043 RemovePred(SU, Pred);
1049 RemovePred(SU, Pred);
1055 RemovePred(SU, Pred);
1061 D.setSUnit(SU);
1073 D.setSUnit(SU);
1097 SU = NewSU;
1100 DEBUG(dbgs() << " Duplicating SU #" << SU->NodeNum << "\n");
1101 NewSU = CreateClone(SU);
1104 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1112 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1121 D.setSUnit(SU);
1128 AvailableQueue->updateNode(SU);
1137 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
1152 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1173 SDep FromDep(SU, SDep::Data, Reg);
1174 FromDep.setLatency(SU->Latency);
1180 AvailableQueue->updateNode(SU);
1207 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg,
1218 if (LiveRegDefs[*AliasI] == SU) continue;
1229 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask,
1236 if (LiveRegDefs[i] == SU) continue;
1257 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) {
1264 // If SU is the currently live definition of the same register that it uses,
1266 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1268 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] != SU)
1273 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) {
1293 CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
1318 CheckForLiveRegDefMasked(SU, RegMask, LiveRegDefs, RegAdded, LRegs);
1324 CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
1333 SUnit *SU = Interferences[i-1];
1334 LRegsMapT::iterator LRegsPos = LRegsMap.find(SU);
1340 SU->isPending = false;
1344 if (SU->isAvailable && !SU->NodeQueueId) {
1345 DEBUG(dbgs() << " Repushing SU #" << SU->NodeNum << '\n');
1346 AvailableQueue->push(SU);
1368 << " SU #" << CurSU->NodeNum << '\n');
1372 CurSU->isPending = true; // This SU is not in AvailableQueue right now.
1414 DEBUG(dbgs() << "ARTIFICIAL edge from SU(" << BtSU->NodeNum << ") to SU("
1464 DEBUG(dbgs() << " Adding an edge from SU #" << TrySU->NodeNum
1465 << " to SU #" << Copies.front()->NodeNum << "\n");
1470 DEBUG(dbgs() << " Adding an edge from SU #" << NewDef->NodeNum
1471 << " to SU #" << TrySU->NodeNum << "\n");
1504 SUnit *SU = PickNodeToScheduleBottomUp();
1506 AdvancePastStalls(SU);
1508 ScheduleNodeBottomUp(SU);
1511 // Advance the cycle to free resources. Skip ahead to the next ready SU.
1536 bool isReady(SUnit* SU, unsigned CurCycle) const { return true; }
1592 bool isReady(SUnit *SU, unsigned CurCycle) const;
1609 bool isReady(SUnit *SU, unsigned CurCycle) const;
1674 void addNode(const SUnit *SU) override;
1676 void updateNode(const SUnit *SU) override;
1684 unsigned getNodePriority(const SUnit *SU) const;
1686 unsigned getNodeOrdering(const SUnit *SU) const {
1687 if (!SU->getNode()) return 0;
1689 return SU->getNode()->getIROrder();
1700 void remove(SUnit *SU) override {
1702 assert(SU->NodeQueueId != 0 && "Not in queue!");
1704 SU);
1708 SU->NodeQueueId = 0;
1715 bool HighRegPressure(const SUnit *SU) const;
1717 bool MayReduceRegPressure(SUnit *SU) const;
1719 int RegPressureDiff(SUnit *SU, unsigned &LiveUses) const;
1721 void scheduledNode(SUnit *SU) override;
1723 void unscheduledNode(SUnit *SU) override;
1726 bool canClobber(const SUnit *SU, const SUnit *Op);
1793 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG);
1794 dbgs() << "Height " << SU->getHeight() << ": ";
1795 SU->dump(DAG);
1835 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) {
1836 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum];
1841 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1870 void RegReductionPQBase::addNode(const SUnit *SU) {
1874 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
1877 void RegReductionPQBase::updateNode(const SUnit *SU) {
1878 SethiUllmanNumbers[SU->NodeNum] = 0;
1879 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
1884 unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const {
1885 assert(SU->NodeNum < SethiUllmanNumbers.size());
1886 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
1897 if (SU->NumSuccs == 0 && SU->NumPreds != 0)
1898 // If SU does not have a register use, i.e. it doesn't produce a value
1904 if (SU->NumPreds == 0 && SU->NumSuccs != 0)
1905 // If SU does not have a register def, schedule it close to its uses
1909 return SethiUllmanNumbers[SU->NodeNum];
1911 unsigned Priority = SethiUllmanNumbers[SU->NodeNum];
1912 if (SU->isCallOp) {
1914 int NP = (int)Priority - SU->getNode()->getNumValues();
1939 bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const {
1943 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
1965 bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const {
1966 const SDNode *N = SU->getNode();
1968 if (!N->isMachineOpcode() || !SU->NumSuccs)
1990 int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const {
1993 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
2013 const SDNode *N = SU->getNode();
2015 if (!N || !N->isMachineOpcode() || !SU->NumSuccs)
2030 void RegReductionPQBase::scheduledNode(SUnit *SU) {
2034 if (!SU->getNode())
2037 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2058 // here with the reduction further below. Note that this SU may use multiple
2078 //assert(SU->NumRegDefsLeft == 0 && "not all regdefs have scheduled uses");
2079 int SkipRegDefs = (int)SU->NumRegDefsLeft;
2080 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(SU, scheduleDAG);
2089 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") has too many regdefs\n");
2099 void RegReductionPQBase::unscheduledNode(SUnit *SU) {
2103 const SDNode *N = SU->getNode();
2119 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2164 if (SU->NumSuccs && N->isMachineOpcode()) {
2186 static unsigned closestSucc(const SUnit *SU) {
2188 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
2205 static unsigned calcMaxScratches(const SUnit *SU) {
2207 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2215 /// hasOnlyLiveInOpers - Return true if SU has only value predecessors that are
2217 static bool hasOnlyLiveInOpers(const SUnit *SU) {
2219 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2237 /// hasOnlyLiveOutUses - Return true if SU has only value successors that are
2238 /// CopyToReg to a virtual register. This SU def is probably a liveout and
2240 static bool hasOnlyLiveOutUses(const SUnit *SU) {
2242 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
2269 static void initVRegCycle(SUnit *SU) {
2273 if (!hasOnlyLiveInOpers(SU) || !hasOnlyLiveOutUses(SU))
2276 DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n");
2278 SU->isVRegCycle = true;
2280 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2289 static void resetVRegCycle(SUnit *SU) {
2290 if (!SU->isVRegCycle)
2293 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
2307 static bool hasVRegCycleUse(const SUnit *SU) {
2308 // If this SU also defines the VReg, don't hoist it as a "use".
2309 if (SU->isVRegCycle)
2312 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
2317 DEBUG(dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n");
2326 // Note: The ScheduleHazardRecognizer interface requires a non-const SU.
2327 static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) {
2329 if (SPQ->getHazardRec()->getHazardType(SU, 0)
2377 DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNum
2378 << ") depth " << LDepth << " vs SU (" << right->NodeNum
2401 DEBUG(dbgs() << " SU (" << left->NodeNum << ") "
2402 << PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum << ") "
2519 bool hybrid_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const {
2522 if (SPQ->MayReduceRegPressure(SU)) return true;
2524 if (SU->getHeight() > (CurCycle + ReadyDelay)) return false;
2526 if (SPQ->getHazardRec()->getHazardType(SU, -ReadyDelay)
2547 DEBUG(dbgs() << " pressure SU(" << left->NodeNum << ") > SU("
2552 DEBUG(dbgs() << " pressure SU(" << right->NodeNum << ") > SU("
2566 bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const {
2567 if (SU->getHeight() > CurCycle) return false;
2569 if (SPQ->getHazardRec()->getHazardType(SU, 0)
2576 static bool canEnableCoalescing(SUnit *SU) {
2577 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
2590 if (SU->NumPreds == 0 && SU->NumSuccs != 0)
2591 // If SU does not have a register def, schedule it close to its uses
2615 DEBUG(dbgs() << "RegPressureDiff SU(" << left->NodeNum << "): " << LPDiff
2616 << " != SU(" << right->NodeNum << "): " << RPDiff << "\n");
2628 DEBUG(dbgs() << "Live uses SU(" << left->NodeNum << "): " << LLiveUses
2629 << " != SU(" << right->NodeNum << "): " << RLiveUses << "\n");
2643 DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): "
2644 << left->getDepth() << " != SU(" << right->NodeNum << "): "
2682 bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) {
2683 if (SU->isTwoAddress) {
2684 unsigned Opc = SU->getNode()->getMachineOpcode();
2690 SDNode *DU = SU->getNode()->getOperand(i).getNode();
2700 /// canClobberReachingPhysRegUse - True if SU would clobber one of it's
2702 /// i.e. DepSU should not be scheduled above SU.
2703 static bool canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU,
2708 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs();
2709 const uint32_t *RegMask = getNodeRegMask(SU->getNode());
2713 for (SUnit::const_succ_iterator SI = SU->Succs.begin(), SE = SU->Succs.end();
2727 // Return true if SU clobbers this physical register use and the
2738 /// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's
2740 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,
2747 for (const SDNode *SUNode = SU->getNode(); SUNode;
2811 SUnit *SU = &(*SUnits)[i];
2815 if (SU->NumSuccs != 0)
2818 if (SU->NumPreds != 1)
2822 if (SDNode *N = SU->getNode())
2830 for (SUnit::const_pred_iterator II = SU->Preds.begin(),
2831 EE = SU->Preds.end(); II != EE; ++II)
2842 // Short-circuit the case where SU is PredSU's only data successor.
2847 if (SDNode *N = SU->getNode())
2857 if (PredSuccSU == SU) continue;
2863 if (SU->hasPhysRegClobbers && PredSuccSU->hasPhysRegDefs)
2864 if (canClobberPhysRegDefs(PredSuccSU, SU, TII, TRI))
2867 if (scheduleDAG->IsReachable(SU, PredSuccSU))
2873 DEBUG(dbgs() << " Prescheduling SU #" << SU->NodeNum
2880 if (SuccSU != SU) {
2883 scheduleDAG->AddPred(SU, Edge);
2884 Edge.setSUnit(SU);
2902 SUnit *SU = &(*SUnits)[i];
2903 if (!SU->isTwoAddress)
2906 SDNode *Node = SU->getNode();
2907 if (!Node || !Node->isMachineOpcode() || SU->getNode()->getGluedNode())
2910 bool isLiveOut = hasOnlyLiveOutUses(SU);
2918 SDNode *DU = SU->getNode()->getOperand(j).getNode();
2927 if (SuccSU == SU)
2931 if (SuccSU->getHeight() < SU->getHeight() &&
2932 (SU->getHeight() - SuccSU->getHeight()) > 1)
2948 if (SuccSU->hasPhysRegDefs && SU->hasPhysRegClobbers) {
2949 if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
2959 if (!canClobberReachingPhysRegUse(SuccSU, SU, scheduleDAG, TII, TRI) &&
2962 (!SU->isCommutable && SuccSU->isCommutable)) &&
2963 !scheduleDAG->IsReachable(SuccSU, SU)) {
2964 DEBUG(dbgs() << " Adding a pseudo-two-addr edge from SU #"
2965 << SU->NodeNum << " to SU #" << SuccSU->NodeNum << "\n");
2966 scheduleDAG->AddPred(SU, SDep(SuccSU, SDep::Artificial));