| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| f80a63fa23862e578de919f4b44d4fcdee68fd0d |
|
28-Sep-2013 |
Robert Wilhelm <robert.wilhelm@gmx.net> |
Fix spelling intruction -> instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3c70fcf02b367f517e93c1bd4ce237966383ebf8 |
|
15-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Add 'const' qualifier to some arrays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| a0ec3f9b7b826b9b40b80199923b664bad808cce |
|
14-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 6a2e7ac0b6647a409394e58b385e579ea62b5cba |
|
06-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Cache the TargetLowering info object as a pointer.
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| dd0fb018a7cd2214c7bc5c6c767f626f99b47ba9 |
|
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 3/4.
Remove the old IR ordering mechanism and switch to new one. Fix unit
test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 61aba54f2c0f432179dfaa758bdb2bf1b9929814 |
|
20-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
Revert "pre-RA-sched: fix TargetOpcode usage"
This reverts commit 06091513c283c863296f01cc7c2e86b56bb50d02.
The code is obviously wrong, but the trivial fix causes
inefficient code generation on X86. Somebody with more
knowledge of the code needs to take a look here.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177529 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 06091513c283c863296f01cc7c2e86b56bb50d02 |
|
20-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
pre-RA-sched: fix TargetOpcode usage
TargetOpcodes need to be treaded as Machine- and not ISD-Opcodes.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 877fcf52d17f1cadc38112ca988cdd4e666bac24 |
|
07-Mar-2013 |
Andrew Trick <atrick@apple.com> |
pre-RA-sched debug-only fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176638 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| ccd38f4efb7f1a4457234d95e30fec5bcc738700 |
|
07-Mar-2013 |
Andrew Trick <atrick@apple.com> |
pre-RA-sched assertion fix. This bug was exposed by r176037.
rdar:13370002 [pre-RA-sched] assertion: released too many times
I tracked this down to an earlier hack that is no longer applicable
and interfered with normal scheduler logic. With the changes in
r176037, it was causing an instruction to be scheduled multiple times.
I have an external test case that I tried hard to reduce and
failed. I can't even reproduce with llc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 029f4fd2ff539ed143b83c140349df2c064965d2 |
|
25-Feb-2013 |
Andrew Trick <atrick@apple.com> |
pre-RA-sched fix: only reevaluate physreg interferences when necessary.
Fixes rdar:13279013: scheduler was blowing up on select instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176037 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| f662a59b8b031bd43e43e0282b58bef920f0793d |
|
29-Jan-2013 |
Weiming Zhao <weimingz@codeaurora.org> |
Add a special handling case for untyped CopyFromReg node in GetCostForDef() of ScheduleDAGRRList
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
|
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 860e7cdab9d5eceda5ac52ae0ddfb4bdab0067f2 |
|
13-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRepRegClassFor to take an MVT, instead of
EVT.
Accordingly, change RegDefIter to contain MVTs instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 34525f9ac098c1c6bc9002886d6da3039a284fd2 |
|
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| aa7744d75fc1769ccc12c65c07bb5b82afa58330 |
|
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRepRegClassFor to take an MVT, instead of
EVT.
Accordingly, change RegDefIter to contain MVTs instead of EVTs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| ae692f2baedf53504af2715993b166950e185a55 |
|
12-Nov-2012 |
Andrew Trick <atrick@apple.com> |
misched: Infrastructure for weak DAG edges.
This adds support for weak DAG edges to the general scheduling
infrastructure in preparation for MachineScheduler support for
heuristics based on weak edges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| a78d3228e8b2a14915ea9908dbaaf2c934803e11 |
|
06-Nov-2012 |
Andrew Trick <atrick@apple.com> |
ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.
This is in preparation for adding "weak" DAG edges, but generally
simplifies the design.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167435 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3574eca1b02600bac4e625297f4ecf745f4c4f32 |
|
08-Oct-2012 |
Micah Villmow <villmow@gmail.com> |
Move TargetData to DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| b720be6a50f4e1b3280d2b029ee38dda14577525 |
|
12-Sep-2012 |
Manman Ren <mren@apple.com> |
Release build: guard dump functions with
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)"
No functional change. Update r163339.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 77e300e8f0b8db8eec448cae9c87d7c5bfad9757 |
|
06-Sep-2012 |
Manman Ren <mren@apple.com> |
Release build: guard dump functions with "ifndef NDEBUG"
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c05d30601ced172b55be81bb529df6be91d6ae15 |
|
06-Sep-2012 |
Nadav Rotem <nrotem@apple.com> |
Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c8e41c591741b3da1077f7000274ad040bef8002 |
|
23-Jul-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Fix a typo (the the => the)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 4eb4e5eb224b3d737558bcda8a0a369cc9d800e6 |
|
05-Jun-2012 |
Andrew Trick <atrick@apple.com> |
sdsched: Use the right heuristics when -mcpu is not provided and we have no itinerary.
Use ILP heuristics for long latency instrs if no scoreboard exists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 396618b43a85e12d290a90b181c6af5d7c0c5f11 |
|
02-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch all register list clients to the new MC*Iterator interface.
No functional change intended.
Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.
This makes it possible to do so without changing all clients (again).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| e32981048244ecfa67d0bdc211af1bac2020a555 |
|
24-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Mark some static arrays as const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 397fc4874efe9c17e737d4c5c50bd19dc3bf27f5 |
|
08-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).
So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.
Patch by Yiannis Tsiouris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 479389a4da53ce72226366cc6d1cad13da158909 |
|
22-Mar-2012 |
Evan Cheng <evan.cheng@apple.com> |
Source order scheduler should not preschedule nodes with multiple uses. rdar://11096639
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| fac259814923d091942b230e7bd002a8d1130bc3 |
|
08-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store instruction implicit uses and defs. Reduces static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 953be893e8cffa0ef9bf410036cd96aeb526e98a |
|
08-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: rename core scheduler methods for consistency.
We had half the API with one convention, half with another. Now was a
good time to clean it up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 73ba69b6843f7f23345b1e8745cb328952cae0d8 |
|
07-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: modularize schedule printing.
ScheduleDAG will not refer to the scheduled instruction sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152205 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 4c727204271067f3dbf50bd23098b2df8e1cc47a |
|
07-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: modularize schedule verification.
ScheduleDAG will not refer to the scheduled instruction sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| e4fd907e72a599eddfa7a81eac4366b5b82523e3 |
|
04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store register overlaps to reduce static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 16a7ff31655aa2de65d86472edcb71cf2df3ac3a |
|
14-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add register mask support to ScheduleDAGRRList.
The scheduler will sometimes check the implicit-def list on instructions
to properly handle pre-colored DAG edges.
Also check any register mask operands for physreg clobbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 0e6307f6423a7ee39b80f8dc3caef00ad11e0266 |
|
07-Dec-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make sure we correctly set LiveRegGens when a call is unscheduled. <rdar://problem/10460321>. No testcase because this is very sensitive to scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146087 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 30c44e18bf28c3f5feda56e97695e2b72de7fedb |
|
07-Dec-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Fix an assertion in the scheduler. PR11386. No testcase included because it's rather delicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| e77ae2d692a25034da908151761c0f6b7e071779 |
|
07-Dec-2011 |
Nick Lewycky <nicholas@mxc.ca> |
These global variables aren't thread-safe, STATISTIC is. Andy Trick tells me
that he isn't using these any more, so just delete them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 99aa14ff64c92eab347d23696e358361d3bd90ea |
|
16-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Rename MVT::untyped to MVT::Untyped to match similar nomenclature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 2d496897934adfc0e3e1563dd64d9a7122971e22 |
|
15-Nov-2011 |
Pete Cooper <peter_cooper@apple.com> |
Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used
by later instructions.
Only done for DEC64m right now.
Fixes <rdar://problem/6172640>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 623a7e146bd86747dc46a6f8bb9993fc217d6b78 |
|
10-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Use a bigger hammer to fix PR11314 by disabling the "forcing two-address
instruction lower optimization" in the pre-RA scheduler.
The optimization, rather the hack, was done before MI use-list was available.
Now we should be able to implement it in a better way, perhaps in the
two-address pass until a MI scheduler is available.
Now that the scheduler has to backtrack to handle call sequences. Adding
artificial scheduling constraints is just not safe. Furthermore, the hack
is not taking all the other scheduling decisions into consideration so it's just
as likely to pessimize code. So I view disabling this optimization goodness
regardless of PR11314.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144267 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| ef0b3ca3a8935b5390633dc7bb4adcdb99e0c26a |
|
09-Nov-2011 |
Duncan Sands <baldrick@free.fr> |
Speculatively revert commit 144124 (djg) in the hope that the 32 bit
dragonegg self-host buildbot will recover (it is complaining about object
files differing between different build stages). Original commit message:
Add a hack to the scheduler to disable pseudo-two-address dependencies in
basic blocks containing calls. This works around a problem in which
these artificial dependencies can get tied up in calling seqeunce
scheduling in a way that makes the graph unschedulable with the current
approach of using artificial physical register dependencies for calling
sequences. This fixes PR11314.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 9cae2d2225ba58a70ef8ff057feab6873f4af520 |
|
08-Nov-2011 |
Dan Gohman <gohman@apple.com> |
Add a hack to the scheduler to disable pseudo-two-address dependencies in
basic blocks containing calls. This works around a problem in which
these artificial dependencies can get tied up in calling seqeunce
scheduling in a way that makes the graph unschedulable with the current
approach of using artificial physical register dependencies for calling
sequences. This fixes PR11314.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 65fd6564b8aedd053845c81ede1ac594acb470e4 |
|
03-Nov-2011 |
Dan Gohman <gohman@apple.com> |
Reapply r143206, with fixes. Disallow physical register lifetimes
across calls, and only check for nested dependences on the special
call-sequence-resource register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 6f3ddef7c51f03945644ad0e69068dfb24d4b092 |
|
29-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Revert r143206, as there are still some failing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| bf923b815d6da97367e3eedab69230918bf128a3 |
|
28-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Reapply r143177 and r143179 (reverting r143188), with scheduler
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 62c1d00dfd38996f381edae55e1028b8e52a1107 |
|
28-Oct-2011 |
Duncan Sands <baldrick@free.fr> |
Speculatively disable Dan's commits 143177 and 143179 to see if
it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
Delete #if 0 code accidentally left in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 2ba60e593012ba9b2a9d20b86733eadca288bcb2 |
|
28-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.
Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.
Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.
Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.
This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 692c1d85353249124caa1885cfeda513146c6d81 |
|
24-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Change this overloaded use of Sched::Latency to be an overloaded
use of Sched::ILP instead, as Sched::Latency is going away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| ec0e5475fdb9d7d3a4d8206d84f469bc83be1cf1 |
|
21-Oct-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Remove a now dead function, fixing -Wunused-function warnings from
Clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142631 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| ff764815e6531be6b2d944bd6a3f1fcfc682db01 |
|
20-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Delete the list-tdrr scheduler. Top-down schedulers are going away
because they don't support physical register dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142620 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 340d78f4e7b95c235d0ecf315b755bebefd0a168 |
|
01-Sep-2011 |
Andrew Trick <atrick@apple.com> |
PreRA scheduler should avoid cloning compares.
Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| e837dead3c8dc3445ef6a0e2322179c57e264a13 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 15993f83a419950f06d2879d6701530ae6449317 |
|
27-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 4ef4c171dba8e479f5f3fe7acb22e9fe97a4d6f8 |
|
27-Jun-2011 |
Andrew Trick <atrick@apple.com> |
pre-RA-sched: Cleanup register pressure tracking.
Removed the check that peeks past EXTRA_SUBREG, which I don't think
makes sense any more. Intead treat it as a normal register def. No
significant affect on x86 or ARM benchmarks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| f792fa90f1125553008659c743cba85b9b5d2e5e |
|
27-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Distinguish early clobber output operands from clobbered registers.
Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we
now use two different asm operand kinds.
The new Kind_Clobber is treated identically to the old
Kind_RegDefEarlyClobber for now, but x87 floating point stack inline
assembly does care about the difference.
This will pop a register off the stack:
asm("fstp %st" : : "t"(x) : "st");
While this will pop the input and push an output:
asm("fst %st" : "=&t"(r) : "t"(x));
We need to know if ST0 was a clobber or an output operand, and we can't
depend on <dead> flags for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133902 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 109c22c06232358597afec5d8b7a6b6fd24e19b1 |
|
22-Jun-2011 |
Owen Anderson <resistor@mac.com> |
Fix some trailing issues from my introduction of MVT::untyped and its use for REGISTER_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 1396c403897e3d3e04fbf59f6c5fe77cbbab74a6 |
|
18-Jun-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove unused but set variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133347 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 77b4b13c2a525faf646a6784b24692cf0459b75e |
|
16-Jun-2011 |
Owen Anderson <resistor@mac.com> |
Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 4cb971ce1c8b254f29365c988b55f6dcfe86d21e |
|
15-Jun-2011 |
Andrew Trick <atrick@apple.com> |
Added -stress-sched flag in the Asserts build.
Added a test case for handling physreg aliases during pre-RA-sched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 8ae3edacfaebfeed3e65bbbcf18a6fb21b09feaf |
|
08-Jun-2011 |
Andrew Trick <atrick@apple.com> |
Remove a temporary test case probe in CheckForLiveRegDef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 9d507aec07c7e22c6ba83dfd75e23c8630cd25cd |
|
07-Jun-2011 |
Andrew Trick <atrick@apple.com> |
Fix a merge bug in preRAsched for handling physreg aliases.
I've been sitting on this long enough trying to find a test case. I
think the fix should go in now, but I'll keep working on the test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 554daa67bd1c4f01fb7a00f2f4255a52b81e9fa3 |
|
26-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Be careful about scheduling nodes above previous calls. It increase usages of
more callee-saved registers and introduce copies. Only allows it if scheduling
a node above calls would end up lessen register pressure.
Call operands also has added ABI restrictions for register allocation, so be
extra careful with hoisting them above calls.
rdar://9329627
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| b16d06f88a81a5163e0caffad4bb268a8e1d0204 |
|
26-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130190 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 12f0dc6bb556976f22d89ebcf42bce273c9e7d38 |
|
14-Apr-2011 |
Andrew Trick <atrick@apple.com> |
In the pre-RA scheduler, maintain cmp+br proximity.
This is done by pushing physical register definitions close to their
use, which happens to handle flag definitions if they're not glued to
the branch. This seems to be generally a good thing though, so I
didn't need to add a target hook yet.
The primary motivation is to generate code closer to what people
expect and rule out missed opportunity from enabling macro-op
fusion. As a side benefit, we get several 2-5% gains on x86
benchmarks. There is one regression:
SingleSource/Benchmarks/Shootout/lists slows down be -10%. But this is
an independent scheduler bug that will be tracked separately.
See rdar://problem/9283108.
Incidentally, pre-RA scheduling is only half the solution. Fixing the
later passes is tracked by:
<rdar://problem/8932804> [pre-RA-sched] on x86, attempt to schedule CMP/TEST adjacent with condition jump
Fixes:
<rdar://problem/9262453> Scheduler unnecessary break of cmp/jump fusion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 87896d9368e08d93493427ce7bf8272d1e5cca35 |
|
13-Apr-2011 |
Andrew Trick <atrick@apple.com> |
Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.
Additional fixes:
Do something reasonable for subtargets with generic
itineraries by handle node latency the same as for an empty
itinerary. Now nodes default to unit latency unless an itinerary
explicitly specifies a zero cycle stage or it is a TokenFactor chain.
Original fixes:
UnitsSharePred was a source of randomness in the scheduler: node
priority depended on the queue data structure. I rewrote the recent
VRegCycle heuristics to completely replace the old heuristic without
any randomness. To make the ndoe latency adjustments work, I also
needed to do something a little more reasonable with TokenFactor. I
gave it zero latency to its consumers and always schedule it as low as
possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c558bf397257f5ef902bdb45a28e622ee2b5b4f2 |
|
12-Apr-2011 |
Andrew Trick <atrick@apple.com> |
Revert 129383. It causes some targets to hit a scheduler assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129385 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3eb4319313b3fb9189cd4be5b3e5375be9bdc2f9 |
|
12-Apr-2011 |
Andrew Trick <atrick@apple.com> |
PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.
UnitsSharePred was a source of randomness in the scheduler: node
priority depended on the queue data structure. I rewrote the recent
VRegCycle heuristics to completely replace the old heuristic without
any randomness. To make these heuristic adjustments to node latency work,
I also needed to do something a little more reasonable with TokenFactor. I
gave it zero latency to its consumers and always schedule it as low as
possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129383 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 54699765064842fd08d1466adc93453660bc2a85 |
|
07-Apr-2011 |
Andrew Trick <atrick@apple.com> |
Added a check in the preRA scheduler for potential interference on a
induction variable. The preRA scheduler is unaware of induction vars,
so we look for potential "virtual register cycles" instead.
Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129100 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 336298cf2cc68d9af163992b9f9cafddd4bb3c8a |
|
25-Mar-2011 |
Andrew Trick <atrick@apple.com> |
Fix for -pre-RA-sched=source.
Yet another case of unchecked NULL node (for physreg copy).
May fix PR9509.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| bd47a4a307a54dab25956430442cf4ac103e4158 |
|
23-Mar-2011 |
Andrew Trick <atrick@apple.com> |
Ensure that def-side physreg copies are scheduled above any other uses
so the scheduler can't create new interferences on the copies
themselves. Prior to this fix the scheduler could get stuck in a loop
creating copies.
Fixes PR9509.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 0d93a110e31b384f59d91d6be27388d8ded5f03c |
|
23-Mar-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128163 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 28ed90b95db5f14b60b2cb532a62d407d4faf5e5 |
|
21-Mar-2011 |
Eric Christopher <echristo@apple.com> |
Grammar-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| b0519e15f70cef7ba16b712f258d4782ade17e13 |
|
10-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit 127368 and 127371. They are exonerated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 02d7c9298298f7f8fba1427f249deb2106126e9c |
|
10-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revert 127368 and 127371 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 17adafc6c179f3bad757f932a13522851ee5171f |
|
09-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be more
flexible.
If it returns a register class that's different from the input, then that's the
register class used for cross-register class copies.
If it returns a register class that's the same as the input, then no cross-
register class copies are needed (normal copies would do).
If it returns null, then it's not at all possible to copy registers of the
specified register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| d7cdc3e1f9df50be73e239c130dc92239c0e5d32 |
|
09-Mar-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix typo, make helper static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 29449448b0f0420dfcf52e278fc01adbf1690d70 |
|
08-Mar-2011 |
Eric Christopher <echristo@apple.com> |
Fix some latent bugs if the nodes are unschedulable. We'd gotten away
with this before since none of the register tracking or nightly tests
had unschedulable nodes.
This should probably be refixed with a special default Node that just
returns some "don't touch me" values.
Fixes PR9427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127263 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 0bf56c821c454a960afc34cb5746006bc1f9e1a1 |
|
08-Mar-2011 |
Andrew Trick <atrick@apple.com> |
Further improvements to pre-RA-sched=list-ilp.
This change uses the MaxReorderWindow for both height and depth, which
tends to limit the negative effects of high register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127203 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| be2119e8e2bc7006cfd638a24367acbfda625d16 |
|
07-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| b43034d700004e1fec3ddf177e21ac89478bcc6c |
|
06-Mar-2011 |
Eric Christopher <echristo@apple.com> |
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3c6e49504e9a57a4818750fd2520967f84634eac |
|
06-Mar-2011 |
Andrew Trick <atrick@apple.com> |
Disable a couple of experimental heuristics to get the best results from the current implementation of -pre-RA-sched=list-ilp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127113 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| afc7d235e91a769f74d87bbe745558ed1b692ff7 |
|
05-Mar-2011 |
Andrew Trick <atrick@apple.com> |
Be explicit with abs(). Visual Studio workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127075 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| ab2e3e2d7074207e2a4bb15e2913fa83795bb1ca |
|
05-Mar-2011 |
Andrew Trick <atrick@apple.com> |
Missing comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127068 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| e0ef509aeb47b396cf1bdc170ca4f468f799719f |
|
05-Mar-2011 |
Andrew Trick <atrick@apple.com> |
Increased the register pressure limit on x86_64 from 8 to 12
regs. This is the only change in this checkin that may affects the
default scheduler. With better register tracking and heuristics, it
doesn't make sense to artificially lower the register limit so much.
Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to
give the scheduler a way to account for div and sqrt on targets that
don't have an itinerary. It is currently defaults to 10 (the actual
number doesn't matter much), but only takes effect on non-default
schedulers: list-hybrid and list-ilp.
Added several heuristics that can be individually disabled for the
non-default sched=list-ilp mode. This helps us determine how much
better we can do on a given benchmark than the default
scheduler. Certain compute intensive loops run much faster in this
mode with the right set of heuristics, and it doesn't seem to have
much negative impact elsewhere. Not all of the heuristics are needed,
but we still need to experiment to decide which should be disabled by
default for sched=list-ilp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| a0807f57caed954545661c23607c507f8d5c3d64 |
|
04-Mar-2011 |
Andrew Trick <atrick@apple.com> |
Minor pre-RA-sched fixes and cleanup.
Fix the PendingQueue, then disable it because it's not required for
the current schedulers' heuristics.
Fix the logic for the unused list-ilp scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 92e946630d5f9bb092853b93501387dd216899b9 |
|
04-Feb-2011 |
Andrew Trick <atrick@apple.com> |
Introducing a new method of tracking register pressure. We can't
precisely track pressure on a selection DAG, but we can at least keep
it balanced. This design accounts for various interesting aspects of
selection DAGS: register and subregister copies, glued nodes, dead
nodes, unused registers, etc.
Added SUnit::NumRegDefsLeft and ScheduleDAGSDNodes::RegDefIter.
Note: I disabled PrescheduleNodesWithMultipleUses when register
pressure is enabled, based on no evidence other than I don't think it
makes sense to have both enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| e787ddb5105b2c355c166c395ddbeb2047cf3136 |
|
27-Jan-2011 |
Andrew Trick <atrick@apple.com> |
Remove a temporary workaround for a lencod miscompile. Depends on the fix in r124442.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124443 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c48d50f9c036b48826e75df125d80af596980e00 |
|
24-Jan-2011 |
Andrew Trick <atrick@apple.com> |
Temporarily workaround JM/lencod miscompile (SIGSEGV).
rdar://problem/8893967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| d1dace8aea073716daf0055ad07fde1164b2a472 |
|
21-Jan-2011 |
Andrew Trick <atrick@apple.com> |
Enable support for precise scheduling of the instruction selection
DAG. Disable using "-disable-sched-cycles".
For ARM, this enables a framework for modeling the cpu pipeline and
counting stalls. It also activates several heuristics to drive
scheduling based on the model. Scheduling is inherently imprecise at
this stage, and until spilling is improved it may defeat attempts to
schedule. However, this framework provides greater control over
tuning codegen.
Although the flag is not target-specific, it should have very little
affect on the default scheduler used by x86. The only two changes that
affect x86 are:
- scheduling a high-latency operation bumps the current cycle so independent
operations can have their latency covered. i.e. two independent 4
cycle operations can produce results in 4 cycles, not 8 cycles.
- Two operations with equal register pressure impact and no
latency-based stalls on their uses will be prioritized by depth before height
(height is irrelevant if no stalls occur in the schedule below this point).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123971 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4 |
|
21-Jan-2011 |
Andrew Trick <atrick@apple.com> |
Convert -enable-sched-cycles and -enable-sched-hazard to -disable
flags. They are still not enable in this revision.
Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with
the scheduler's model of operand latency in the selection DAG.
Generalized unit tests to work with sched-cycles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 0bc308600b0069f07ba722b472c68588573ebd28 |
|
20-Jan-2011 |
Andrew Trick <atrick@apple.com> |
Selection DAG scheduler register pressure heuristic fixes.
Added a check for already live regs before claiming HighRegPressure.
Fixed a few cases of checking the wrong number of successors.
Added some tracing until these heuristics are better understood.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| f697c8a19adf962a933b055383952e72789a0e20 |
|
14-Jan-2011 |
Andrew Trick <atrick@apple.com> |
Support for precise scheduling of the instruction selection DAG,
disabled in this checkin. Sorry for the large diffs due to
refactoring. New functionality is all guarded by EnableSchedCycles.
Scheduling the isel DAG is inherently imprecise, but we give it a best
effort:
- Added MayReduceRegPressure to allow stalled nodes in the queue only
if there is a regpressure need.
- Added BUHasStall to allow checking for either dependence stalls due to
latency or resource stalls due to pipeline hazards.
- Added BUCompareLatency to encapsulate and standardize the heuristics
for minimizing stall cycles (vs. reducing register pressure).
- Modified the bottom-up heuristic (now in BUCompareLatency) to
prioritize nodes by their depth rather than height. As long as it
doesn't stall, height is irrelevant. Depth represents the critical
path to the DAG root.
- Added hybrid_ls_rr_sort::isReady to filter stalled nodes before
adding them to the available queue.
Related Cleanup: most of the register reduction routines do not need
to be templates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| a75ce9f5d2236d93c117e861e60e6f3f748c9555 |
|
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Minor cleanup related to my latest scheduler changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122545 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 24312230ada6f4cfa8776351dafb12eea8a81b33 |
|
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Fix a few cases where the scheduler is not checking for phys reg copies. The scheduling node may have a NULL DAG node, yuck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122544 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 2da8bc8a5f7705ac131184cd247f48500da0d74e |
|
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 29d8f0cae425f1bba583565227eaebf58f26ce73 |
|
23-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
flags -> glue for selectiondag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122509 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 2902736a507df1c6fdc0daa4e8f0e385bb5f7820 |
|
23-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Reorganize ListScheduleBottomUp in preparation for modeling machine cycles and instruction issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122491 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3d420cb2fee925d0888cd3a60a222a19e75cd890 |
|
23-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Converted LiveRegCycles to LiveRegGens. It's easier to work with and allows multiple nodes per cycle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122474 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| cb7947b81be4cb55fc647ea3722eb7a8613545cb |
|
23-Dec-2010 |
Andrew Trick <atrick@apple.com> |
In CheckForLiveRegDef use TRI->getOverlaps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122473 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 1b1658741aa4bc88fc488ef217d9603294e16c58 |
|
23-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Fixes PR8823: add-with-overflow-128.ll
In the bottom-up selection DAG scheduling, handle two-address
instructions that read/write unspillable registers. Treat
the entire chain of two-address nodes as a single live range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122472 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| feac09801b5c03412d452e685570baff6eb84c88 |
|
21-Dec-2010 |
Andrew Trick <atrick@apple.com> |
In DelayForLiveRegsBottomUp, handle instructions that read and write
the same physical register. Simplifies the fix from the previous
checkin r122211.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 38036d8b36fa5d1b2f3530f47fd716e9da7bffab |
|
21-Dec-2010 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| f1b4eafbfec976f939ec0ea3e8acf91cef5363e3 |
|
21-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 37944985a569f8c2b0d75dafd9e2739a9887ac5d |
|
20-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
Fix a bug in the scheduler's handling of "unspillable" vregs.
Imagine we see:
EFLAGS = inst1
EFLAGS = inst2 FLAGS
gpr = inst3 EFLAGS
Previously, we would refuse to schedule inst2 because it clobbers
the EFLAGS of the predecessor. However, it also uses the EFLAGS
of the predecessor, so it is safe to emit. SDep edges ensure that
the right order happens already anyway.
This fixes 2 testsuite crashes with the X86 patch I'm going to
commit next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122211 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 142d21c861c0b686e38a515b1271f4157cd24004 |
|
20-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
the result of CheckForLiveRegDef is dead, remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122209 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 8239daf7c83a65a189c352cce3191cdc3bbfe151 |
|
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Two sets of changes. Sorry they are intermingled.
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 089751535d6e9adf65842e2ca5867bf9a70e1e95 |
|
29-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoiding overly aggressive latency scheduling. If the two nodes share an
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.
BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB
=>
BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB
This fixed the recent 256.bzip2 regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| e0e925efb31ca98c78e53bf52db8529388a0390a |
|
26-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
The "excess register pressure" returned by HighRegPressure() is not accurate enough to factor into scheduling priority. Eliminate it and add early exits to speed up scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109449 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| b3893b193b294c4dfd37e101e9d796568b28d461 |
|
26-Jul-2010 |
Duncan Sands <baldrick@free.fr> |
Pacify gcc-4.5 which wrongly thinks that RExcess (passed as the Excess parameter)
may be used uninitialized in the callers of HighRegPressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109393 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| e28ed16d2507633893269670d289006f3e0b351e |
|
25-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109383 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3f92f73970862c1926b4c70fe097c979de5f02d0 |
|
25-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix crashes when scheduling a CopyToReg node -- getMachineOpcode asserts on
those. Radar 8231572.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109367 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 70017e44cdba1946cc478ce1856a3e855a767e28 |
|
24-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add an ILP scheduler. This is a register pressure aware scheduler that's
appropriate for targets without detailed instruction iterineries.
The scheduler schedules for increased instruction level parallelism in
low register pressure situation; it schedules to reduce register pressure
when the register pressure becomes high.
On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2
by 16%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3144687df78731ac4ddbc716a24b951678a73f57 |
|
24-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Allow target to specify when is register pressure "too high". In most cases,
it's too late to start backing off aggressive latency scheduling when most
of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
For ARM, this is almost always a win on # of instructions. It's runtime
neutral for most of the tests. But for some kernels with high register
pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
54 and sped up by 20%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 89ba74d117577f5a1bd62ee209dc2ecb090172e3 |
|
22-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply r109079 with fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 8b9177aee2671568182e1688e1c53f2459038e46 |
|
22-Jul-2010 |
Owen Anderson <resistor@mac.com> |
Revert r109079, which broke a lot of CodeGen tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| a4081238aa51eb16a46a2da78438ff476798f34d |
|
22-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Initialize RegLimit only when register pressure is being tracked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109079 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 4a863e2c75145432fd660ee65e61b578c5e90ac9 |
|
22-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
More register pressure aware scheduling work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 4f6b4674be5473319ac5e70c76fd5cb964da2128 |
|
21-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| d31f972bd33de85071c716f69bf5c6d735f730f2 |
|
29-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
of getPhysicalRegisterRegClass with it.
If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 10e02a017a877b750d4cdf0ebf11b90dee5e0d61 |
|
30-May-2010 |
Oscar Fuentes <ofv@wanadoo.es> |
Use `llvm::next' instead of `next' to make VC++ 2010 happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 046fa3f90a31ebfa10df89ae348f478d492709a9 |
|
29-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix some latency computation bugs: if the use is not a machine opcode do not just return zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 93d343357944beb701d425fc7ef00dd7b0a32bd7 |
|
26-May-2010 |
Dan Gohman <gohman@apple.com> |
Eliminate the use of PriorityQueue and just use a std::vector,
implementing pop with a linear search for a "best" element. The priority
queue was a neat idea, but in practice the comparison functions depend
on dynamic information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| d89c2580510b8f79394039987f0ad84dee903e59 |
|
26-May-2010 |
Dan Gohman <gohman@apple.com> |
Delete an unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104716 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| a4e4ffd389497eb28f5fe91521fb71da4340e5d6 |
|
26-May-2010 |
Dan Gohman <gohman@apple.com> |
Change push_all to a non-virtual function and implement it in the
base class, since all the implementations are the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| b11ac950d69c7a238de0a22fd23fbfcd994f57ee |
|
21-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104306 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 1cc3984148be113c6e5e470f23c9ddbd37679c5f |
|
21-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 15a16def6e70c8f7df1023da80ceb89887203b40 |
|
20-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add a hybrid bottom up scheduler that reduce register usage while avoiding
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104216 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| decc2671516e6c52ee2f29f7746f8d02753845ea |
|
07-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
Three changes:
1. Introduce some enums and accessors in the InlineAsm class
that eliminate a ton of magic numbers when handling inline
asm SDNode.
2. Add a new MDNodeSDNode selection dag node type that holds
a MDNode (shocking!)
3. Add a new argument to ISD::INLINEASM nodes that hold !srcloc
metadata, propagating it to the instruction emitter, which
drops it.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100605 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 518bb53485df640d7b7e3f6b0544099020c42aa7 |
|
09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 5ba8bf6d28ad350114a4b02f01d70ebe08612cfe |
|
05-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
When the scheduler unfold a load folding instruction it move some of the predecessors to the unfolded load. It decides what gets moved to the load by checking whether the new load is using the predecessor as an operand. The check neglects the cases whether the predecessor is a flagged scheduling unit.
rdar://7604000
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 187361b056823df4ff292561fe47468dad956872 |
|
23-Jan-2010 |
Bill Wendling <isanbard@gmail.com> |
Remove the '-disable-scheduling' flag and replace it with the 'source' option of
the '-pre-RA-sched' flag. It actually makes more sense to do it this way. Also,
keep track of the SDNode ordering by default. Eventually, we would like to make
this ordering a way to break a "tie" in the scheduler. However, doing that now
breaks the "CodeGen/X86/abi-isel.ll" test for 32-bit Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3f09487404bc46297dc6fd91ca3ac478c3a7fa34 |
|
06-Jan-2010 |
Bill Wendling <isanbard@gmail.com> |
The previous code could potentially cause a cycle. Allow ordering w.r.t. a 0 order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| cfeea4b92aa5be102e58efea947ca40a95b0c999 |
|
06-Jan-2010 |
Bill Wendling <isanbard@gmail.com> |
Only check the ordering if there is an ordering for each nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92807 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 247fb4ebd363323b6642ce2bb08e53db705ca094 |
|
06-Jan-2010 |
Bill Wendling <isanbard@gmail.com> |
Add a semi-primitive form of scheduling via the "SDNode ordering" to the
bottom-up scheduler. We prefer the lower order number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| e492ae13edd83b120d665c0503cf4de2925b5e56 |
|
05-Jan-2010 |
David Greene <greened@obbligato.org> |
Change errs() to dbgs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92576 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| f5a86f45e75ec744c203270ffa03659eb0a220c1 |
|
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 6726b6d75a8b679068a58cb954ba97cf9d1690ba |
|
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 98976e4dcd18adbbe676048c0069e67346eb4ade |
|
10-Oct-2009 |
Dan Gohman <gohman@apple.com> |
The ScheduleDAG framework now requires an AliasAnalysis argument, though
it isn't needed in the ScheduleDAGSDNodes schedulers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3a90c9b8edb53ea1ea57d94f7ab256608b5b30c6 |
|
30-Sep-2009 |
Reid Kleckner <reid@kleckner.net> |
Silence comparison always false warning in -Asserts mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c277ab08a24d2dbe9b4ff1a9154ea6115ed6a4e3 |
|
30-Sep-2009 |
Reid Kleckner <reid@kleckner.net> |
Fix integer overflow in instruction scheduling. This can happen if we have
basic blocks that are so long that their size overflows a short.
Also assert that overflow does not happen in the future, as requested by Evan.
This fixes PR4401.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 4437ae213d5435390f0750213b53ec807c047f22 |
|
23-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate uses of cerr()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79834 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| bbbfa99d3d18fe9f20265305e833666645ada528 |
|
23-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
remove a few DOUTs here and there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| e50ed30282bb5b4a9ed952580523f2dda16215ac |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c23197a26f34f559ea9797de51e187087c039c42 |
|
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c25e7581b9b8088910da31702d4ca21c4734c6d7 |
|
11-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 98a366d547772010e94609e4584489b3e5ce0043 |
|
30-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Instead of passing in an unsigned value for the optimization level, use an enum,
which better identifies what the optimization is doing. And is more flexible for
future uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| be8cc2a3dedeb7685f07e68cdc4b9502eb97eb2b |
|
29-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Second attempt:
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70343 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c69d56f1154342a57c9bdd4c17a10333e3520127 |
|
28-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
r70270 isn't ready yet. Back this out. Sorry for the noise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 2e9d5f912a9841d3685ba0241abe1131943fed29 |
|
28-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 0e4042d30b2b47329166f5f784ef3c70f6b408cc |
|
16-Apr-2009 |
Dan Gohman <gohman@apple.com> |
In the list-burr's pseudo two-addr dependency heuristics, don't
add dependencies on nodes with exactly one successor which is a
COPY_TO_REGCLASS node. In the case that the copy is coalesced
away, the dependence should be on the user of the copy, rather
than the copy itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69309 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 8af808a3d64dfdcc5d126e6ad762f57b1483671c |
|
16-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Handle SUBREG_TO_REG instructions with the same heuristics
as INSERT_SUBREG instructions in the list-burr scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 8f4aa333d02d0f48f90f4604d894a73ee53edcb5 |
|
24-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Minor compile-time optimization; don't bother checking
canClobberPhysRegDefs if the successor node doesn't
clobber any physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 002b44f1d7c0b301b78dec1f24d406d4b351fdaa |
|
24-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Add a pre-pass to the burr-list scheduler which makes adjustments to
help out the register pressure reduction heuristics in the case of
nodes with multiple uses. Currently this uses very conservative
heuristics, so it doesn't have a broad impact, but in cases where it
does help it can make a big difference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67586 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| fa9afef7eaa0865fb9f3489a68a04332b232ed82 |
|
23-Mar-2009 |
Dan Gohman <gohman@apple.com> |
When unfolding a load during scheduling, the new operator node has
a data dependency on the load node, so it really needs a
data-dependence edge to the load node, even if the load previously
existed.
And add a few comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67554 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| a5c8ae233ebaef270b8fa96565ca7bf4fdcb3e15 |
|
23-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Fix canClobberPhysRegDefs to check all SDNodes grouped together
in an SUnit, instead of just the first one. This fix is needed
by some upcoming scheduler changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 697cbbfb00c318f98d6eb51945f077e2bfe8781e |
|
20-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
For inline asm output operand that matches an input. Encode the input operand index in the high bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67387 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| b398fca15bcca895526699f20336fa6c6a624013 |
|
13-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 16e8eda4b8b0825d38ba37d31c99edba0fb25482 |
|
06-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Fix ScheduleDAGRRList::CopyAndMoveSuccessors' handling of nodes
with multiple chain operands. This can occur when the scheduler
has added chain operands to a node that already has a chain
operand, in order to handle physical register dependencies.
This fixes an llvm-gcc bootstrap failure on x86-64 introduced
in r66058.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66240 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 599a6a88ce1925a6349ac7af9a9638aad1d832cc |
|
04-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| f2b14715d11e52adbb17a5860d1ce42f82f85a0c |
|
12-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Oops. Last second clean up messed things up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 8182347d70413174f2e80ea429801e887aee5cc3 |
|
12-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Replace one of burr scheduling heuristic with something more sensible. Now calcMaxScratches simply compute the number of true data dependencies. This actually improve a couple of tests in dejagnu suite as many tests in llvm nightly test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c7fa16f782b0ef1d51bff0f88bffbbe37d03adf5 |
|
11-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Fix a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c8db34cb07fea88c4b8f3e0f095fd8aed568b28e |
|
11-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Don't use special heuristics for nodes with no data predecessors
unless they actually have data successors, and likewise for nodes
with no data successors unless they actually have data precessors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64327 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| cc994ea36bd6f501334d8be4219fc23caff025d9 |
|
11-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Delete the heuristic for non-livein CopyFromReg nodes. Non-liveinness
is determined by whether the node has a Flag operand. However, if the
node does have a Flag operand, it will be glued to its register's
def, so the heuristic would end up spuriously applying to whatever
node is the def.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64319 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 47ac0f0c7c39289f5970688154e385be22b7f293 |
|
11-Feb-2009 |
Dan Gohman <gohman@apple.com> |
When scheduling a block in parts, keep track of the overall
instruction index across each part. Instruction indices are used
to make live range queries, and live ranges can extend beyond
scheduling region boundaries.
Refactor the ScheduleDAGSDNodes class some more so that it
doesn't have to worry about this additional information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 9e64bbb322417c09f27afdf08e3946287c9df5aa |
|
11-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Factor out more code for computing register live-range informationfor
scheduling, and generalize is so that preserves state across
scheduling regions. This fixes incorrect live-range information around
terminators and labels, which are effective region boundaries.
In place of looking for terminators to anchor inter-block dependencies,
introduce special entry and exit scheduling units for this purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64254 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| f0e366a929a1acb4bc14df5ef831cce74607a967 |
|
10-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR3457: Ignore control successors when looking for closest scheduled successor. A control successor doesn't read result(s) produced by the scheduling unit being evaluated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64210 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 84fbac580941548a6ab1121ed3b0ffdc4e2bc080 |
|
06-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Move ScheduleDAGSDNodes.h to be a private header. Front-ends
that previously included this header should include
SchedulerRegistry.h instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63937 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 1cc6b8ee787c183a7c88fec8fbb96c1404cf34e8 |
|
29-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Make a few things const, fix some comments, and simplify
some assertions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 79ce276083ced01256a0eb7d80731e4948ca6e87 |
|
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.
To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| bc0b56732a2d1dc22767e0f3930f22a76d99470a |
|
13-Jan-2009 |
Dan Gohman <gohman@apple.com> |
The list-td and list-tdrr schedulers don't yet support physreg
scheduling dependencies. Add assertion checks to help catch
this.
It appears the Mips target defaults to list-td, and it has a
regression test that uses a physreg dependence. Such code was
liable to be miscompiled, and now evokes an assertion failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c29a56dedbe4297dad94b9bf2e19035c5903fd1f |
|
12-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR3241: Currently EmitCopyFromReg emits a copy from the physical register to a virtual register unless it requires an expensive cross class copy. That means we are only treating "expensive to copy" register dependency as physical register dependency.
Also future proof the scheduler to handle "normal" physical register dependencies. The code is not exercised yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62074 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 84036a77a36a934514e51c99f83e6c3632bf98f5 |
|
09-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Minor debug output tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62005 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 25fd4037a7f698877eedb69bf32d8591344e86ee |
|
07-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Remove redundant 'else's. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61891 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| ce0d4b7a77da716f234d42edd0472e97b3ba5f57 |
|
06-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Update these argument lists for the isNormalMemory
argument. This doesn't affect current functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| fd2163bcf77df6b3e58868483c089bd3869b01d6 |
|
06-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Use a latency value of 0 for the artificial edges inserted by
AddPseudoTwoAddrDeps. This lets the scheduling infrastructure
avoid recalculating node heights. In very large testcases this
was a major bottleneck. Thanks to Roman Levenstein for finding
this!
As a side effect, fold-pcmpeqd-0.ll is now scheduled better
and it no longer requires spilling on x86-32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| d68a07650cdb2e18f18f362ba533459aa10e01b6 |
|
05-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Tidy up #includes, deleting a bunch of unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 1eb9268080498bc7b6d2d5df6fe8c13d6f939de0 |
|
03-Jan-2009 |
Dan Gohman <gohman@apple.com> |
CommuteNodesToReducePressure() is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61612 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 223942a420cf5b9e888524186134cc652be8a921 |
|
03-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Remove the code from the scheduler that commuted two-address
instructions to avoid copies, because TwoAddressInstructionPass
also does this optimization. The scheduler's version didn't
account for live-out values, which resulted in spurious commutes
and missed opportunities.
Now, TwoAddressInstructionPass handles all the opportunities,
instead of just those that the scheduler missed. The result is
usually the same, though there are occasional trivial differences
resulting from the avoidance of spurious commutes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c9a5b9e38b442c2ae6b115213a07df3fcd14708d |
|
23-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Rename BuildSchedUnits to BuildSchedGraph, and refactor the
code in ScheduleDAGSDNodes' BuildSchedGraph into separate functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3f23744df4809eba94284e601e81489212c974d4 |
|
16-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Fix some register-alias-related bugs in the post-RA scheduler liveness
computation code. Also, avoid adding output-depenency edges when both
defs are dead, which frequently happens with EFLAGS defs.
Compute Depth and Height lazily, and always in terms of edge latency
values. For the schedulers that don't care about latency, edge latencies
are set to 1.
Eliminate Cycle and CycleBound, and LatencyPriorityQueue's Latencies array.
These are all subsumed by the Depth and Height fields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| ffa391272bad598d73fd5404dadf3686b69f2a63 |
|
16-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Make addPred and removePred return void, since the return value is not
currently used by anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 54e4c36a7349e94a84773afb56eccd4ca65b49e9 |
|
09-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Rewrite the SDep class, and simplify some of the related code.
The Cost field is removed. It was only being used in a very limited way,
to indicate when the scheduler should attempt to protect a live register,
and it isn't really needed to do that. If we ever want the scheduler to
start inserting copies in non-prohibitive situations, we'll have to
rethink some things anyway.
A Latency field is added. Instead of giving each node a single
fixed latency, each edge can have its own latency. This will eventually
be used to model various micro-architecture properties more accurately.
The PointerIntPair class and an internal union are now used, which
reduce the overall size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| b29ffc88701fc373c832ea2e7142ad6f72eef050 |
|
04-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Make debug output more informative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 21d9003087c9a707e6cd95460136b499df358fb8 |
|
25-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Initial support for anti-dependence breaking. Currently this code does not
introduce any new spilling; it just uses unused registers.
Refactor the SUnit topological sort code out of the RRList scheduler and
make use of it to help with the post-pass scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 942b8c853375ae6a3e84f4b0a70f6d4e194ea594 |
|
24-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Check in the rest of this change. The isAntiDep flag needs to be passed
to removePred because an SUnit can both data-depend and anti-depend
on the same SUnit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| cddd428459a66830b0d072823f94224ace58e625 |
|
21-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Add a flag to SDep for tracking which edges are anti-dependence edges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59785 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 98adea11496400c8385b774b4d9f9acd4c99d254 |
|
21-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDep's isSpecial to isArtificial, to make this field a little
less mysterious.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| f209c2cc301ed762e4314536137832ee26e65be0 |
|
21-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Remove the CycleBound computation code from the ScheduleDAGRRList
schedulers. This doesn't have much immediate impact because
targets that use these schedulers by default don't yet provide
pipeline information.
This code also didn't have the benefit of register pressure
information. Also, removing it will avoid problems with list-burr
suddenly starting to do latency-oriented scheduling on x86 when we
start providing pipeline data, which would increase spilling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59775 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 47d1a214a7013d12140a0c4972d7ba761150dfd4 |
|
21-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Change these schedulers to not emit no-ops. It turns out that
the RR scheduler actually does look at latency values, but it
doesn't use a hazard recognizer so it has no way to know when
a no-op is needed, as opposed to just stalling and incrementing
the cycle count.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 57bebbbd1229040ad659ef4671a34e8d1d78a6f6 |
|
20-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Remove a remnant of list-burr's fast mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 117f3e9ee426ab7eb120b5ca1b65763baae2a824 |
|
20-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Factor out the SethiUllman numbering logic from the list-burr and
list-tdrr schedulers into a common base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 9e76fea3abd4229749e6ead46a0016cabff4a056 |
|
20-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Remove the "fast" form of the list-burr scheduler, and use the
dedicated "fast" scheduler in -fast mode instead, which is
faster. This speeds up llc -fast by a few percent on some
testcases -- the speedup only happens for code not handled by
fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 6be2ee431f44e3eb4d87bb3779a7e97a766c7a3e |
|
20-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Facter AddPseudoTwoAddrDeps and associated infrasructure out of
the list-burr scheduler so that it can be used by the list-tdrr
scheduler too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59698 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| a1e6d363e5efa9eb1a2e7ac21a0394c870bef5ad |
|
20-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Factor out the code for verifying the work of the scheduler,
extend it a bit, and make use of it in all schedulers, to
ensure consistent checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59689 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 343f0c046702831a4a6aec951b6a297a23241a55 |
|
20-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Experimental post-pass scheduling support. Post-pass scheduling
is currently off by default, and can be enabled with
-disable-post-RA-scheduler=false.
This doesn't have a significant impact on most code yet because it doesn't
yet do anything to address anti-dependencies and it doesn't attempt to
disambiguate memory references. Also, several popular targets
don't have pipeline descriptions yet.
The majority of the changes here are splitting the SelectionDAG-specific
code out of ScheduleDAG, so that ScheduleDAG can be moved to
libLLVMCodeGen.a. The interface between ScheduleDAG-using code and
the rest of the scheduling code is somewhat rough and will evolve.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c2f9062ea4915ae034417eaeead3c5942921f24d |
|
19-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Rearrange code to reduce the nesting level. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 1256f5fe769ab2cced36abf2cbf9e1f63f22282d |
|
18-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Tidy up ScheduleNodeBottomUp methods, and make them more
consistent with ScheduleNodeTopDown methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59550 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3cc6243ddfdba3ad64035b919c88b09773a60880 |
|
18-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Change SUnit's dump method to take a ScheduleDAG* instead of
a SelectionDAG*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 2d093f356007979e2e071725a98894a36c3625e0 |
|
18-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Avoid using a loop in ReleasePred and ReleaseSucc methods to compute the
new CycleBound value. Instead, just update CycleBound on each call.
Also, make ReleasePred and ReleaseSucc methods more consistent accross
the various schedulers.
This also happens to make ScheduleDAGRRList's CycleBound computation
somewhat more interesting, though it still doesn't have any noticeable
effect, because no current targets that use the register-pressure
reduction scheduler provide pipeline models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 8123419f2be881ca77a897918f28514aa4e91765 |
|
17-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Eliminate some trivial differences between the ScheduleNodeTopDown
functions in these two schedulers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| d23e0f81bc76902052e9198cad3a0d87a412a632 |
|
14-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Remove the FlaggedNodes member from SUnit. Instead of requiring each SUnit
to carry a SmallVector of flagged nodes, just calculate the flagged nodes
dynamically when they are needed.
The local-liveness change is due to a trivial scheduling change where
the scheduler arbitrary decision differently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 550f5afb68ce8f034991863cac65bef22a6554da |
|
13-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Make the Node member of SUnit private, and add accessors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| a23b3b803e3c65e84d6cadaa221de8b256cbe28d |
|
13-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Change ScheduleDAG's DAG member from a reference to a pointer, to prepare
for the possibility of scheduling without a SelectionDAG being present.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59263 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| b13af2f2ec2fd8dc215136cf8783d70225b59f66 |
|
11-Nov-2008 |
Dan Gohman <gohman@apple.com> |
In ScheduleDAGRRList::CopyAndMoveSuccessors, create the SUnit for the load
before creating the SUnit for the operation that it was unfolded from. This
allows each SUnit to have all of its predecessor SUnits available at the time
it is created. I don't know yet if this will be absolutely required, but it
is a little tidier to do it this way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 9b75b373756288cd39489da7994207f50b31ee40 |
|
11-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Change the scheduler accessor methods to accept an explicit TargetMachine
argument instead of taking the SelectionDAG's TargetMachine. This is
needed for some upcoming scheduler changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 87e82f00adb6628ed6368db1eac7d944489287ff |
|
31-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Remove some unused virtual function bodies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| b8cab9227a0f6ffbdaae33e3c64268e265008a6a |
|
14-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Fix command-line option printing to print two spaces where needed,
instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 086ec9976ff6cee083de618429c78473491d5713 |
|
23-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Replace the LiveRegs SmallSet with a simple counter that keeps
track of the number of live registers, which is all the set was
being used for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56498 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 59932584a812685b16ad6a53a023b2bb3fc21819 |
|
17-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Don't worry about clobbering physical register defs that aren't used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| ba36cb5242eb02b12b277f82b9efe497f7da4d7f |
|
28-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| e5a8dc5cc4647cdfd97c71165d4c8f805b4c78a3 |
|
27-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Optimize ScheduleDAGRRList's topological sort to use one pass instead
of two, and to not need a scratch std::vector. Also, compute the ordering
immediately in the result array, instead of in another scratch std::vector
that is copied to the result array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 99a6cb92d173c142073416c81efe6d3daeb80b49 |
|
27-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
disallow direct access to SDValue::ResNo, provide a getter instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 04f4f4f447806cd92a2fb6f4b66d11f6d5003a82 |
|
12-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Correct the filename in the top-of-file comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54688 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 430b8a22e2717d3dfb6b4f096bc23c9538fd7959 |
|
05-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Fix several const-correctness issues, resolving some -Wcast-qual warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54349 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 475871a144eb604ddaf37503397ba0941442e5fb |
|
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| e8be6c63915e0389f1eef6b53c64300d13b2ce99 |
|
17-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.
Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.
This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.
These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 5e84368b26415b3bb7f3f8d9cff3e05938dd82d0 |
|
14-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Reapply 53476 and 53480, with a fix so that it properly updates
the BB member to the current basic block after emitting
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| b5eec33dcde63bee6048d54bee2a376737028e5c |
|
12-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Back out 53476 and 53480 for now. Somehow they cause llc to miscompile 179.art.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 0f4012f4759a6c6ca28f11ed1eb98feb8ab1481b |
|
12-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Factor out debugging code into the common base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| dbe2a5a26925cd3ed8a4c2cf02c8273fcf9919d7 |
|
11-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Add support for putting NamedRegionTimers in TimerGroups, and
use a timer group for the timers in SelectionDAGISel. Also,
Split scheduling out from emitting, to give each their own
timer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c6be777208f4539af400ac694d9d1dc8b992bc80 |
|
02-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
- Use a faster priority comparison function if -fast.
- Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 4576f6d7a9c0f2c6a3b6c5d4d8a3063bbf763ae5 |
|
01-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Do not use computationally expensive scheduling heuristics with -fast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52971 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 8cb8245cf117fc4a4f0a6549d9a773a12895550c |
|
23-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Move a DenseMap's declaration outside of a loop, and just call
clear() on each iteration. This avoids allocating and deallocating
all of DenseMap's memory on each iteration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 2f1d3108e481758da66662f72673741da86312da |
|
22-Jun-2008 |
Dan Gohman <gohman@apple.com> |
canClobberPhysRegDefs shouldn't called without checking hasPhysRegDefs;
check this with an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 94d7a5f8156e62532870fbaf197377b34e52ff2a |
|
21-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Remove ScheduleDAG's SUnitMap altogether. Instead, use SDNode's NodeId
field, which is otherwise unused after instruction selection, as an index
into the SUnit array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52583 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3627e34486db088661bc7fb6c0dde6a18a543217 |
|
21-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Add a priority queue class, which is a wrapper around std::priority_queue
and provides fairly efficient removal of arbitrary elements. Switch
ScheduleDAGRRList from std::set to this new priority queue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 4c8c83022b501759d8559e224c84ae2a9921ba41 |
|
21-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Change ScheduleDAG's SUnitMap from DenseMap<SDNode*, vector<SUnit*> >
to DenseMap<SDNode*, SUnit*>, and adjust the way cloned SUnit nodes are
handled so that only the original node needs to be in the map.
This speeds up llc on 447.dealII.llvm.bc by about 2%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52576 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 16c6859651d08946b769ad44f163216ad124175a |
|
21-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Simplify some template parameterization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb |
|
06-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 419cafb9fb6e77487197933714abec0426ae06c0 |
|
16-May-2008 |
Duncan Sands <baldrick@free.fr> |
Silence the compiler warning differently. The
original method caused gcc-4.2 to complain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 50871247216dfef8386a112766e972a1792b0b56 |
|
14-May-2008 |
Evan Cheng <evan.cheng@apple.com> |
Silence some compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51115 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| a0201d52049be8dcefffe4304a49690a831bcb34 |
|
29-Apr-2008 |
Roman Levenstein <romix.llvm@googlemail.com> |
Use std::set instead of std::priority_queue for the RegReductionPriorityQueue.
This removes the existing bottleneck related to the removal of elements from
the middle of the queue.
Also fixes a subtle bug in ScheduleDAGRRList::CapturePred:
It was updating the state of the SUnit before removing it. As a result, the
comparison operators were working incorrectly and this SUnit could not be removed
from the queue properly.
Reviewed by Evan and Dan. Approved by Dan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50412 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 5a2d335c4cdc2bf870f04b8ca20c8032638d1961 |
|
16-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Fix the new scheduler assertion checks to work when
the scheduler has inserted no-ops. This fixes
the 2006-07-03-schedulers.ll regression on ppc32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 80792f3ddec43aff7f0758c9096f8cb53dcc1e40 |
|
15-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Treat EntryToken nodes as "passive" so that they aren't added to the
ScheduleDAG; they don't correspond to any actual instructions so they
don't need to be scheduled.
This fixes a bug where the EntryToken was being scheduled multiple
times in some cases, though it ended up not causing any trouble because
EntryToken doesn't expand into anything. With this fixed the schedulers
reliably schedule the expected number of units, so we can check this
with an assertion.
This requires a tweak to test/CodeGen/X86/loop-hoist.ll because it
ends up getting scheduled differently in a trivial way, though it was
enough to fool the prcontext+grep that the test does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| fd5da6c991ad0bb5c0b6ce797d56c49ad3f73803 |
|
29-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Cosmetic changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 2a88a5c92f898623d5cceb6cd1019427a1749999 |
|
28-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
ifdef out a dead function. Should this be removed?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48916 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| d7d3ea00c0a26e2545d4ba01825d8358075264e7 |
|
27-Mar-2008 |
Roman Levenstein <romix.llvm@googlemail.com> |
Fix spelling. Thanks, Duncan! :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 95d4184e7218d7ec21b5b8d693dd3b14146eefdc |
|
27-Mar-2008 |
Roman Levenstein <romix.llvm@googlemail.com> |
Speed-up the SumOfUnscheduledPredsOfSuccs by introducing a new function
called LimitedSumOfUnscheduledPredsOfSuccs. It terminates the computation
after a given treshold is reached. This new function is always faster, but
brings real wins only on bigger test-cases.
The old function SumOfUnscheduledPredsOfSuccs is left in-place for now and therefore a warning about an unused static function is produced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48872 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 8dba9afd086f72db920db81a3d73c7297390cda7 |
|
26-Mar-2008 |
Roman Levenstein <romix.llvm@googlemail.com> |
Fixed some spelling errors. Thanks, Duncan!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48819 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| e513ba49589bcf8fdf7dad658e20db21d6ef4758 |
|
26-Mar-2008 |
Roman Levenstein <romix.llvm@googlemail.com> |
Some improvements related to the computation of isReachable.
This fixes Bugzilla #1835 (http://llvm.org/bugs/show_bug.cgi?id=1835).
This patched is reviewed by Tanya and Dan. Dan tested and approved it.
The reason for the bad performance of the old algorithm is that it is very naive and scans every
time all nodes of the DAG in the worst case.
This patch introduces a new algorithm based on the paper "Online algorithms
for maintaining the topological order of a directed acyclic graph" by
David J.Pearce and Paul H.J.Kelly. This is the MNR algorithm. It has a
linear time worst-case and performs much better in most situations.
The paper can be found here:
http://fano.ics.uci.edu/cites/Document/Online-algorithms-for-maintaining-the-topological-order-of-a-directed-acyclic-graph.html
The main idea of the new algorithm is to compute the topological ordering of the SNodes in the
DAG and to maintain it even after DAG modifications. The topological ordering allows for very fast
node reachability checks.
Tests on very big input files with tens of thousands of instructions in a BB indicate huge
speed-ups (up to 10x compilation time improvement) compared to the old version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48817 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| cffbd2562a5e3ba435dd2b622710ec272c634da5 |
|
25-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Fix typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 676dd7c80b6f91178452535ac45ca58feb23cc42 |
|
11-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 917be6814e0a4e529d290be5d806a054bbbc4a27 |
|
04-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename isOperand() to isOperandOf() (and other similar methods). It always confuses me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47872 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 84d4a2b4ad0874a46642bb568b45720d55e46b64 |
|
01-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Refactor / clean up code; remove td list scheduler special tie breaker (no real benefit).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 4c71dfe356716e6bc1993ef5efdced08b68fe612 |
|
20-Feb-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Update gcc 4.3 warnings fix patch with recent head changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 94ebde1d45dcd7e209663c49a1cf1a4589191df1 |
|
16-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Revert 47177, which was incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 53c607f562a74d9374bd390a4be151a952ba5d29 |
|
15-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Skip over the defs and start at the uses when looking for operands
with the TIED_TO attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3b66555c53eb8921b2dd50335e0b278ddf80d220 |
|
15-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Use the TargetInstrDescr to determine the number of operands
that should be checked for the TIED_TO attribute instead of
using CountOperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47176 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 6f0d024a534af18d9e60b3ea757376cd8a3a980e |
|
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 303595942502f17c087fa28874c2b89117148c45 |
|
29-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Use empty() instead of comparing size() with zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46514 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 9f65c39f806186e1bbe1c9e4b670d198c69a81c1 |
|
29-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 6ee9661390849bd9564cda38bfbe563ec255c419 |
|
29-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 19107563af7568713193c60be24503446556bff2 |
|
10-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Special copy SUnit's do not have SDNode's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 749c6f6b5ed301c84aac562e414486549d7b98eb |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3db805ea80eeec9084a1b86273d93804d233d938 |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
simplify some code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 0ff23966feb90618bec4d085095ffbc28426e691 |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Rename all the M_* flags to be namespace qualified enums, and switch
all clients over to using predicates instead of these flags directly.
These are now private values which are only to be used to statically
initialize the tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 349c4952009525b27383e2120a6b3c998f39bd09 |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 6425f8be7263e625c2d7484eb2fb8f6643824f49 |
|
07-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Update CodeGen for MRegisterInfo --> TargetInstrInfo changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 84bc5427d6883f73cfeae3da640acd011d35c006 |
|
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 180c210a1d96a56ae0611d4f8de81e1ada5559eb |
|
20-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
More accurate checks for two-address constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| d6c0758944b31bb5316b36cad37f4610a77f784d |
|
20-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
Bring back a burr scheduling heuristic that's still needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45252 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| beec823d4bba22b1c0c6658d2b3e71cd64a70e2e |
|
18-Dec-2007 |
Evan Cheng <evan.cheng@apple.com> |
FIX for PR1799: When a load is unfolded from an instruction, check if it is a new node. If not, do not create a new SUnit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45157 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 7da8f399bf09e9a03fe8bdd8c8eef6e5a7d87327 |
|
09-Nov-2007 |
Evan Cheng <evan.cheng@apple.com> |
Bug fix. Passive nodes are not in SUnitMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 1fd15ba9614e81a3b9cc5cd9631ca76c845159b2 |
|
06-Nov-2007 |
Evan Cheng <evan.cheng@apple.com> |
Add pseudo dependency to force two-address instruction to be scheduled after
other uses. There was a overly restricted check that prevented some obvious
cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 01d029b82cb08367d81aa10cdc94d05360466649 |
|
15-Oct-2007 |
Chris Lattner <sabre@nondot.org> |
One mundane change: Change ReplaceAllUsesOfValueWith to *optionally*
take a deleted nodes vector, instead of requiring it.
One more significant change: Implement the start of a legalizer that
just works on types. This legalizer is designed to run before the
operation legalizer and ensure just that the input dag is transformed
into an output dag whose operand and result types are all legal, even
if the operations on those types are not.
This design/impl has the following advantages:
1. When finished, this will *significantly* reduce the amount of code in
LegalizeDAG.cpp. It will remove all the code related to promotion and
expansion as well as splitting and scalarizing vectors.
2. The new code is very simple, idiomatic, and modular: unlike
LegalizeDAG.cpp, it has no 3000 line long functions. :)
3. The implementation is completely iterative instead of recursive, good
for hacking on large dags without blowing out your stack.
4. The implementation updates nodes in place when possible instead of
deallocating and reallocating the entire graph that points to some
mutated node.
5. The code nicely separates out handling of operations with invalid
results from operations with invalid operands, making some cases
simpler and easier to understand.
6. The new -debug-only=legalize-types option is very very handy :),
allowing you to easily understand what legalize types is doing.
This is not yet done. Until the ifdef added to SelectionDAGISel.cpp is
enabled, this does nothing. However, this code is sufficient to legalize
all of the code in 186.crafty, olden and freebench on an x86 machine. The
biggest issues are:
1. Vectors aren't implemented at all yet
2. SoftFP is a mess, I need to talk to Evan about it.
3. No lowering to libcalls is implemented yet.
4. Various operations are missing etc.
5. There are FIXME's for stuff I hax0r'd out, like softfp.
Hey, at least it is a step in the right direction :). If you'd like to help,
just enable the #ifdef in SelectionDAGISel.cpp and compile code with it. If
this explodes it will tell you what needs to be implemented. Help is
certainly appreciated.
Once this goes in, we can do three things:
1. Add a new pass of dag combine between the "type legalizer" and "operation
legalizer" passes. This will let us catch some long-standing isel issues
that we miss because operation legalization often obfuscates the dag with
target-specific nodes.
2. We can rip out all of the type legalization code from LegalizeDAG.cpp,
making it much smaller and simpler. When that happens we can then
reimplement the core functionality left in it in a much more efficient and
non-recursive way.
3. Once the whole legalizer is non-recursive, we can implement whole-function
selectiondags maybe...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 32dfbeada7292167bb488f36a71a5a6a519ddaff |
|
12-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
EXTRACT_SUBREG coalescing support. The coalescer now treats EXTRACT_SUBREG like
(almost) a register copy. However, it always coalesced to the register of the
RHS (the super-register). All uses of the result of a EXTRACT_SUBREG are sub-
register uses which adds subtle complications to load folding, spiller rewrite,
etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 2eb4ebd953314d7c7f96cfb5897d8ded94f6c9d4 |
|
05-Oct-2007 |
Dan Gohman <gohman@apple.com> |
Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| d5cb5a462b6fd91bf54116c3eefc3b046489c414 |
|
05-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Chain producing nodes cannot be moved, not chain reading nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42627 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 117c3662192bb8590255b0f4435d8e31e5656a57 |
|
05-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Oops. Didn't mean to leave this in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| f10c973797cf79da802f9b0118543cbd50954c9c |
|
05-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
If a node that defines a physical register that is expensive to copy. The
scheduler will try a number of tricks in order to avoid generating the
copies. This may not be possible in case the node produces a chain value
that prevent movement. Try unfolding the load from the node before to allow
it to be moved / cloned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 22a529990bb4bb86bdb2ae1cfce7340320a6ca7f |
|
29-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
If two instructions are both two-address code, favors (schedule closer to
terminator) the one that has a CopyToReg use. This fixes
2006-05-11-InstrSched.ll with -new-cc-modeling-scheme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| ddde335cb79d67c46c04b2a0ffd18750b6f70e28 |
|
28-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove a poor scheduling heuristic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42443 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 74d2fd8dd847e0ebccef30e2c5907ff09495d518 |
|
28-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Trim some unneeded fields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42442 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| cd1c00cc6521c265784ffc7a1b5baf4ef64d80bc |
|
27-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Avoid inserting a live register more than once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 2dc7a0e075f619ecd657acdb19c4be8af051e35c |
|
27-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Boogs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42388 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| a2ee2756f7f80d24312d6ac41b4f2ae548441cac |
|
27-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Be smarter about which node to force schedule. Reduce # of duplications + copies; Added statistics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42387 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 6e4c46cea5daef8bc807a36ce2ab9bb7f9855b67 |
|
27-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Backtracking only when it won't create a cycle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42384 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 42d60274eaa70f8cdbed76d04d25d7a8fc1237cb |
|
26-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
- Move getPhysicalRegisterRegClass() from ScheduleDAG to MRegisterInfo.
- Added ability to emit cross class register copies to the BBRU scheduler.
- More aggressive backtracking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| a6fb1b6743ee1411accf2d6e636f73f2ee0a7f5b |
|
25-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added major new capabilities to scheduler (only BURR for now) to support physical register dependency. The BURR scheduler can now backtrace and duplicate instructions in order to avoid "expensive / impossible to copy" values (e.g. status flag EFLAGS for x86) from being clobbered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 713a98dee8ab07a3066d1707a07648d27dd0c19c |
|
19-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Use struct SDep instead of std::pair for SUnit pred and succ lists. First step
in tracking physical register output dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 66003775464ad01fc828ba3bfaae75759b3f18e8 |
|
13-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Bug fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 8d1bfad00b1ebff5b140b6e1bd7e26bad697d6e1 |
|
20-Aug-2007 |
Dan Gohman <gohman@apple.com> |
Minor cleanups to reduce some spurious differences between different
scheduler implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| e7e7d0d7e39d0c7c659d26b97e8081fce0fcd749 |
|
13-Jul-2007 |
Dale Johannesen <dalej@apple.com> |
Skeleton of post-RA scheduler; doesn't do anything yet.
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 821262953af418649e49e52009f9d3ddae5736c2 |
|
29-Jun-2007 |
David Greene <greened@obbligato.org> |
Remove unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| a2a488594df335efa17bc253436465c2ae984f91 |
|
29-Jun-2007 |
David Greene <greened@obbligato.org> |
Remove unnecessary attributions in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37799 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| a4ab2e8c726e1702d74eb207536bf953bd3d5c81 |
|
29-Jun-2007 |
David Greene <greened@obbligato.org> |
Remove the "special tie breaker" because it resulted in inconsistent
ordering and thus violated the strict weak ordering requirement of
priority_queue. Uncovered by _GLIBCXX_DEBUG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 0b2ce1fc19c5f8742051cf022ac119a3d4d9a3ad |
|
22-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
std::set is really really terrible. Switch to SmallPtrSet to reduce compile time. For Duraid's example. The overall isel time is reduced from 0.6255 sec to 0.1876 sec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| edc1d159841fd279d58177bfd6ac4bc1f616d91a |
|
26-Apr-2007 |
Dan Gohman <gohman@apple.com> |
Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c6deb3d44707de57e82e16642ab845bc8b9e9e01 |
|
14-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Estimate a cost using the possible number of scratch registers required and use
it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35109 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 61230d18d21a5dca1378e994f43934e4b314e595 |
|
14-Mar-2007 |
Evan Cheng <evan.cheng@apple.com> |
Try schedule def + use closer whne Sethi-Ullman numbers are the same.
e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4
Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2
This creates more short live intervals which work better with the register
allocator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 2ba528b3a75955c960347e5b5b28ae74d5a81909 |
|
03-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
switch the sched unit map over to use a DenseMap instead of std::map. This
speeds up isel as a whole time by 2.6%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| fea997aac5773e936754de5436029c2a4fa1e930 |
|
01-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
Fit in 80 columns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c8edc64188399437f5476d7fa45f714a92f2cb93 |
|
09-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Naming consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| c62d4bb6952a1459f10aa93579e1b881d42a33ea |
|
09-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix for PR1075: bottom-up register-reduction scheduling actually increases register pressure.
- Fixed bugs in sethi-ullman number computation and priority queue comparison
functions.
- Separate code that handles priority computation special cases from SU number computation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 832171cb9724d2d31c8dfb73172e2be8f6dd13ee |
|
07-Dec-2006 |
Bill Wendling <isanbard@gmail.com> |
Removing even more <iostream> includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| ba59a1e453e110f7b84233f07613f9c5d9a39b87 |
|
01-Dec-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match TargetInstrInfo changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| d5ad440f4371448e2c926b4f6613cc7107dd5c5c |
|
06-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove dead code; added a missing null ptr check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 95f6edeff5ab6de9cf5589f662c8e7a6ba119c2c |
|
04-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Changes to use operand constraints to process two-address instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 02cb49ee679f60662220fca4e26df4f9f16db5e0 |
|
03-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
silence warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3ed469ccd7b028a030b550d84b7336d146f5d8fa |
|
02-Nov-2006 |
Reid Spencer <rspencer@reidspencer.com> |
For PR786:
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 1dabb68ab45cb05a2c50e9a6f18f60cd3d7105f4 |
|
01-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 93467e7fe3ba5cb60dec94b3ae8cdb13e51aa9a2 |
|
01-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
CopyFromReg starts a live range so its use should not be considered a floater.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31356 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| d42a5238a967c9cdfec8fe086bd18876bff5a951 |
|
14-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Debug tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| a4f0b3a084d120cfc5b5bb06f64b222f5cb72740 |
|
27-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29911 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 228a18e0f220fb85ee06fd5bfa29304e57047ff1 |
|
17-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
switch the SUnit pred/succ sets from being std::sets to being smallvectors.
This reduces selectiondag time on kc++ from 5.43s to 4.98s (9%). More
significantly, this speeds up the default ppc scheduler from ~1571ms to 1063ms,
a 33% speedup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| eb577ba3b815a1fa4627b060dd2345d17abf672d |
|
02-Aug-2006 |
Jim Laskey <jlaskey@mac.com> |
Final polish on machine pass registries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 9ff542f2cce5bf7bf3cf9f692cf3ec0690ad2b3b |
|
01-Aug-2006 |
Jim Laskey <jlaskey@mac.com> |
1. Change use of "Cache" to "Default".
2. Added argument to instruction scheduler creators so the creators can do
special things.
3. Repaired target hazard code.
4. Misc.
More to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 13ec702c430b91ee49b9e6d9581cd95412f216c8 |
|
01-Aug-2006 |
Jim Laskey <jlaskey@mac.com> |
Introducing plugable register allocators and instruction schedulers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29434 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 60f09928a0d22d5927ff0a40fe9163cf1ba1014a |
|
21-Jul-2006 |
Jim Laskey <jlaskey@mac.com> |
Use an enumeration to eliminate data relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29249 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 9525528a7dc5462b6374d38c81ba5c07b11741fe |
|
29-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Use hidden visibility to make symbols in an anonymous namespace get
dropped. This shrinks libllvmgcc.dylib another 67K
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| f8c68f694c25b1ae8c0e5adb2a19432cb405d232 |
|
29-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Shave another 27K off libllvmgcc.dylib with visibility hidden
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28973 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 6b8e5a93183ab08811b7b71887d8c7d774666210 |
|
30-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Make sure the register pressure reduction schedulers work for non-uniform
latency targets, e.g. PPC32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 3b788238683396671e63cad36298d26eb4806dbe |
|
25-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Turn on -sched-commute-nodes by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 8820ad5154eae194a685a8735bd5999221fdffd0 |
|
13-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fixing 2006-05-01-SchedCausingSpills.ll; some clean up
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 07000c6f01d8f57170f2d4c77a86d934bdc5c696 |
|
12-May-2006 |
Owen Anderson <resistor@mac.com> |
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| 13d41b9d721f98372b97d2ec119e6c91932ab0ae |
|
12-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Add capability to scheduler to commute nodes for profit.
If a two-address code whose first operand has uses below, it should be commuted
when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|
| e165a78551a91d8420cd8f074d97701e8788f8b5 |
|
12-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Refactor scheduler code. Move register-reduction list scheduler to a
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
|