ScheduleDAGRRList.cpp revision f2b14715d11e52adbb17a5860d1ce42f82f85a0c
1//===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements bottom-up and top-down register pressure reduction list 11// schedulers, using standard algorithms. The basic approach uses a priority 12// queue of available nodes to schedule. One at a time, nodes are taken from 13// the priority queue (thus in priority order), checked for legality to 14// schedule, and emitted if legal. 15// 16//===----------------------------------------------------------------------===// 17 18#define DEBUG_TYPE "pre-RA-sched" 19#include "ScheduleDAGSDNodes.h" 20#include "llvm/CodeGen/SchedulerRegistry.h" 21#include "llvm/CodeGen/SelectionDAGISel.h" 22#include "llvm/Target/TargetRegisterInfo.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetInstrInfo.h" 26#include "llvm/Support/Debug.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/ADT/PriorityQueue.h" 29#include "llvm/ADT/SmallSet.h" 30#include "llvm/ADT/Statistic.h" 31#include "llvm/ADT/STLExtras.h" 32#include <climits> 33using namespace llvm; 34 35STATISTIC(NumBacktracks, "Number of times scheduler backtracked"); 36STATISTIC(NumUnfolds, "Number of nodes unfolded"); 37STATISTIC(NumDups, "Number of duplicated nodes"); 38STATISTIC(NumPRCopies, "Number of physical register copies"); 39 40static RegisterScheduler 41 burrListDAGScheduler("list-burr", 42 "Bottom-up register reduction list scheduling", 43 createBURRListDAGScheduler); 44static RegisterScheduler 45 tdrListrDAGScheduler("list-tdrr", 46 "Top-down register reduction list scheduling", 47 createTDRRListDAGScheduler); 48 49namespace { 50//===----------------------------------------------------------------------===// 51/// ScheduleDAGRRList - The actual register reduction list scheduler 52/// implementation. This supports both top-down and bottom-up scheduling. 53/// 54class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAGSDNodes { 55private: 56 /// isBottomUp - This is true if the scheduling problem is bottom-up, false if 57 /// it is top-down. 58 bool isBottomUp; 59 60 /// AvailableQueue - The priority queue to use for the available SUnits. 61 SchedulingPriorityQueue *AvailableQueue; 62 63 /// LiveRegDefs - A set of physical registers and their definition 64 /// that are "live". These nodes must be scheduled before any other nodes that 65 /// modifies the registers can be scheduled. 66 unsigned NumLiveRegs; 67 std::vector<SUnit*> LiveRegDefs; 68 std::vector<unsigned> LiveRegCycles; 69 70 /// Topo - A topological ordering for SUnits which permits fast IsReachable 71 /// and similar queries. 72 ScheduleDAGTopologicalSort Topo; 73 74public: 75 ScheduleDAGRRList(MachineFunction &mf, 76 bool isbottomup, 77 SchedulingPriorityQueue *availqueue) 78 : ScheduleDAGSDNodes(mf), isBottomUp(isbottomup), 79 AvailableQueue(availqueue), Topo(SUnits) { 80 } 81 82 ~ScheduleDAGRRList() { 83 delete AvailableQueue; 84 } 85 86 void Schedule(); 87 88 /// IsReachable - Checks if SU is reachable from TargetSU. 89 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { 90 return Topo.IsReachable(SU, TargetSU); 91 } 92 93 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will 94 /// create a cycle. 95 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { 96 return Topo.WillCreateCycle(SU, TargetSU); 97 } 98 99 /// AddPred - adds a predecessor edge to SUnit SU. 100 /// This returns true if this is a new predecessor. 101 /// Updates the topological ordering if required. 102 void AddPred(SUnit *SU, const SDep &D) { 103 Topo.AddPred(SU, D.getSUnit()); 104 SU->addPred(D); 105 } 106 107 /// RemovePred - removes a predecessor edge from SUnit SU. 108 /// This returns true if an edge was removed. 109 /// Updates the topological ordering if required. 110 void RemovePred(SUnit *SU, const SDep &D) { 111 Topo.RemovePred(SU, D.getSUnit()); 112 SU->removePred(D); 113 } 114 115private: 116 void ReleasePred(SUnit *SU, const SDep *PredEdge); 117 void ReleasePredecessors(SUnit *SU, unsigned CurCycle); 118 void ReleaseSucc(SUnit *SU, const SDep *SuccEdge); 119 void ReleaseSuccessors(SUnit *SU); 120 void CapturePred(SDep *PredEdge); 121 void ScheduleNodeBottomUp(SUnit*, unsigned); 122 void ScheduleNodeTopDown(SUnit*, unsigned); 123 void UnscheduleNodeBottomUp(SUnit*); 124 void BacktrackBottomUp(SUnit*, unsigned, unsigned&); 125 SUnit *CopyAndMoveSuccessors(SUnit*); 126 void InsertCopiesAndMoveSuccs(SUnit*, unsigned, 127 const TargetRegisterClass*, 128 const TargetRegisterClass*, 129 SmallVector<SUnit*, 2>&); 130 bool DelayForLiveRegsBottomUp(SUnit*, SmallVector<unsigned, 4>&); 131 void ListScheduleTopDown(); 132 void ListScheduleBottomUp(); 133 134 135 /// CreateNewSUnit - Creates a new SUnit and returns a pointer to it. 136 /// Updates the topological ordering if required. 137 SUnit *CreateNewSUnit(SDNode *N) { 138 unsigned NumSUnits = SUnits.size(); 139 SUnit *NewNode = NewSUnit(N); 140 // Update the topological ordering. 141 if (NewNode->NodeNum >= NumSUnits) 142 Topo.InitDAGTopologicalSorting(); 143 return NewNode; 144 } 145 146 /// CreateClone - Creates a new SUnit from an existing one. 147 /// Updates the topological ordering if required. 148 SUnit *CreateClone(SUnit *N) { 149 unsigned NumSUnits = SUnits.size(); 150 SUnit *NewNode = Clone(N); 151 // Update the topological ordering. 152 if (NewNode->NodeNum >= NumSUnits) 153 Topo.InitDAGTopologicalSorting(); 154 return NewNode; 155 } 156 157 /// ForceUnitLatencies - Return true, since register-pressure-reducing 158 /// scheduling doesn't need actual latency information. 159 bool ForceUnitLatencies() const { return true; } 160}; 161} // end anonymous namespace 162 163 164/// Schedule - Schedule the DAG using list scheduling. 165void ScheduleDAGRRList::Schedule() { 166 DOUT << "********** List Scheduling **********\n"; 167 168 NumLiveRegs = 0; 169 LiveRegDefs.resize(TRI->getNumRegs(), NULL); 170 LiveRegCycles.resize(TRI->getNumRegs(), 0); 171 172 // Build the scheduling graph. 173 BuildSchedGraph(); 174 175 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) 176 SUnits[su].dumpAll(this)); 177 Topo.InitDAGTopologicalSorting(); 178 179 AvailableQueue->initNodes(SUnits); 180 181 // Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate. 182 if (isBottomUp) 183 ListScheduleBottomUp(); 184 else 185 ListScheduleTopDown(); 186 187 AvailableQueue->releaseState(); 188} 189 190//===----------------------------------------------------------------------===// 191// Bottom-Up Scheduling 192//===----------------------------------------------------------------------===// 193 194/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to 195/// the AvailableQueue if the count reaches zero. Also update its cycle bound. 196void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { 197 SUnit *PredSU = PredEdge->getSUnit(); 198 --PredSU->NumSuccsLeft; 199 200#ifndef NDEBUG 201 if (PredSU->NumSuccsLeft < 0) { 202 cerr << "*** Scheduling failed! ***\n"; 203 PredSU->dump(this); 204 cerr << " has been released too many times!\n"; 205 assert(0); 206 } 207#endif 208 209 // If all the node's successors are scheduled, this node is ready 210 // to be scheduled. Ignore the special EntrySU node. 211 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) { 212 PredSU->isAvailable = true; 213 AvailableQueue->push(PredSU); 214 } 215} 216 217void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU, unsigned CurCycle) { 218 // Bottom up: release predecessors 219 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 220 I != E; ++I) { 221 ReleasePred(SU, &*I); 222 if (I->isAssignedRegDep()) { 223 // This is a physical register dependency and it's impossible or 224 // expensive to copy the register. Make sure nothing that can 225 // clobber the register is scheduled between the predecessor and 226 // this node. 227 if (!LiveRegDefs[I->getReg()]) { 228 ++NumLiveRegs; 229 LiveRegDefs[I->getReg()] = I->getSUnit(); 230 LiveRegCycles[I->getReg()] = CurCycle; 231 } 232 } 233 } 234} 235 236/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending 237/// count of its predecessors. If a predecessor pending count is zero, add it to 238/// the Available queue. 239void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { 240 DOUT << "*** Scheduling [" << CurCycle << "]: "; 241 DEBUG(SU->dump(this)); 242 243 assert(CurCycle >= SU->getHeight() && "Node scheduled below its height!"); 244 SU->setHeightToAtLeast(CurCycle); 245 Sequence.push_back(SU); 246 247 ReleasePredecessors(SU, CurCycle); 248 249 // Release all the implicit physical register defs that are live. 250 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 251 I != E; ++I) { 252 if (I->isAssignedRegDep()) { 253 if (LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) { 254 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!"); 255 assert(LiveRegDefs[I->getReg()] == SU && 256 "Physical register dependency violated?"); 257 --NumLiveRegs; 258 LiveRegDefs[I->getReg()] = NULL; 259 LiveRegCycles[I->getReg()] = 0; 260 } 261 } 262 } 263 264 SU->isScheduled = true; 265 AvailableQueue->ScheduledNode(SU); 266} 267 268/// CapturePred - This does the opposite of ReleasePred. Since SU is being 269/// unscheduled, incrcease the succ left count of its predecessors. Remove 270/// them from AvailableQueue if necessary. 271void ScheduleDAGRRList::CapturePred(SDep *PredEdge) { 272 SUnit *PredSU = PredEdge->getSUnit(); 273 if (PredSU->isAvailable) { 274 PredSU->isAvailable = false; 275 if (!PredSU->isPending) 276 AvailableQueue->remove(PredSU); 277 } 278 279 ++PredSU->NumSuccsLeft; 280} 281 282/// UnscheduleNodeBottomUp - Remove the node from the schedule, update its and 283/// its predecessor states to reflect the change. 284void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { 285 DOUT << "*** Unscheduling [" << SU->getHeight() << "]: "; 286 DEBUG(SU->dump(this)); 287 288 AvailableQueue->UnscheduledNode(SU); 289 290 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 291 I != E; ++I) { 292 CapturePred(&*I); 293 if (I->isAssignedRegDep() && SU->getHeight() == LiveRegCycles[I->getReg()]) { 294 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!"); 295 assert(LiveRegDefs[I->getReg()] == I->getSUnit() && 296 "Physical register dependency violated?"); 297 --NumLiveRegs; 298 LiveRegDefs[I->getReg()] = NULL; 299 LiveRegCycles[I->getReg()] = 0; 300 } 301 } 302 303 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 304 I != E; ++I) { 305 if (I->isAssignedRegDep()) { 306 if (!LiveRegDefs[I->getReg()]) { 307 LiveRegDefs[I->getReg()] = SU; 308 ++NumLiveRegs; 309 } 310 if (I->getSUnit()->getHeight() < LiveRegCycles[I->getReg()]) 311 LiveRegCycles[I->getReg()] = I->getSUnit()->getHeight(); 312 } 313 } 314 315 SU->setHeightDirty(); 316 SU->isScheduled = false; 317 SU->isAvailable = true; 318 AvailableQueue->push(SU); 319} 320 321/// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in 322/// BTCycle in order to schedule a specific node. 323void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, unsigned BtCycle, 324 unsigned &CurCycle) { 325 SUnit *OldSU = NULL; 326 while (CurCycle > BtCycle) { 327 OldSU = Sequence.back(); 328 Sequence.pop_back(); 329 if (SU->isSucc(OldSU)) 330 // Don't try to remove SU from AvailableQueue. 331 SU->isAvailable = false; 332 UnscheduleNodeBottomUp(OldSU); 333 --CurCycle; 334 } 335 336 assert(!SU->isSucc(OldSU) && "Something is wrong!"); 337 338 ++NumBacktracks; 339} 340 341/// CopyAndMoveSuccessors - Clone the specified node and move its scheduled 342/// successors to the newly created node. 343SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { 344 if (SU->getNode()->getFlaggedNode()) 345 return NULL; 346 347 SDNode *N = SU->getNode(); 348 if (!N) 349 return NULL; 350 351 SUnit *NewSU; 352 bool TryUnfold = false; 353 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 354 MVT VT = N->getValueType(i); 355 if (VT == MVT::Flag) 356 return NULL; 357 else if (VT == MVT::Other) 358 TryUnfold = true; 359 } 360 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 361 const SDValue &Op = N->getOperand(i); 362 MVT VT = Op.getNode()->getValueType(Op.getResNo()); 363 if (VT == MVT::Flag) 364 return NULL; 365 } 366 367 if (TryUnfold) { 368 SmallVector<SDNode*, 2> NewNodes; 369 if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes)) 370 return NULL; 371 372 DOUT << "Unfolding SU # " << SU->NodeNum << "\n"; 373 assert(NewNodes.size() == 2 && "Expected a load folding node!"); 374 375 N = NewNodes[1]; 376 SDNode *LoadNode = NewNodes[0]; 377 unsigned NumVals = N->getNumValues(); 378 unsigned OldNumVals = SU->getNode()->getNumValues(); 379 for (unsigned i = 0; i != NumVals; ++i) 380 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i)); 381 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals-1), 382 SDValue(LoadNode, 1)); 383 384 // LoadNode may already exist. This can happen when there is another 385 // load from the same location and producing the same type of value 386 // but it has different alignment or volatileness. 387 bool isNewLoad = true; 388 SUnit *LoadSU; 389 if (LoadNode->getNodeId() != -1) { 390 LoadSU = &SUnits[LoadNode->getNodeId()]; 391 isNewLoad = false; 392 } else { 393 LoadSU = CreateNewSUnit(LoadNode); 394 LoadNode->setNodeId(LoadSU->NodeNum); 395 ComputeLatency(LoadSU); 396 } 397 398 SUnit *NewSU = CreateNewSUnit(N); 399 assert(N->getNodeId() == -1 && "Node already inserted!"); 400 N->setNodeId(NewSU->NodeNum); 401 402 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); 403 for (unsigned i = 0; i != TID.getNumOperands(); ++i) { 404 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) { 405 NewSU->isTwoAddress = true; 406 break; 407 } 408 } 409 if (TID.isCommutable()) 410 NewSU->isCommutable = true; 411 ComputeLatency(NewSU); 412 413 SDep ChainPred; 414 SmallVector<SDep, 4> ChainSuccs; 415 SmallVector<SDep, 4> LoadPreds; 416 SmallVector<SDep, 4> NodePreds; 417 SmallVector<SDep, 4> NodeSuccs; 418 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 419 I != E; ++I) { 420 if (I->isCtrl()) 421 ChainPred = *I; 422 else if (I->getSUnit()->getNode() && 423 I->getSUnit()->getNode()->isOperandOf(LoadNode)) 424 LoadPreds.push_back(*I); 425 else 426 NodePreds.push_back(*I); 427 } 428 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 429 I != E; ++I) { 430 if (I->isCtrl()) 431 ChainSuccs.push_back(*I); 432 else 433 NodeSuccs.push_back(*I); 434 } 435 436 if (ChainPred.getSUnit()) { 437 RemovePred(SU, ChainPred); 438 if (isNewLoad) 439 AddPred(LoadSU, ChainPred); 440 } 441 for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) { 442 const SDep &Pred = LoadPreds[i]; 443 RemovePred(SU, Pred); 444 if (isNewLoad) { 445 AddPred(LoadSU, Pred); 446 } 447 } 448 for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) { 449 const SDep &Pred = NodePreds[i]; 450 RemovePred(SU, Pred); 451 AddPred(NewSU, Pred); 452 } 453 for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) { 454 SDep D = NodeSuccs[i]; 455 SUnit *SuccDep = D.getSUnit(); 456 D.setSUnit(SU); 457 RemovePred(SuccDep, D); 458 D.setSUnit(NewSU); 459 AddPred(SuccDep, D); 460 } 461 for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) { 462 SDep D = ChainSuccs[i]; 463 SUnit *SuccDep = D.getSUnit(); 464 D.setSUnit(SU); 465 RemovePred(SuccDep, D); 466 if (isNewLoad) { 467 D.setSUnit(LoadSU); 468 AddPred(SuccDep, D); 469 } 470 } 471 if (isNewLoad) { 472 AddPred(NewSU, SDep(LoadSU, SDep::Order, LoadSU->Latency)); 473 } 474 475 if (isNewLoad) 476 AvailableQueue->addNode(LoadSU); 477 AvailableQueue->addNode(NewSU); 478 479 ++NumUnfolds; 480 481 if (NewSU->NumSuccsLeft == 0) { 482 NewSU->isAvailable = true; 483 return NewSU; 484 } 485 SU = NewSU; 486 } 487 488 DOUT << "Duplicating SU # " << SU->NodeNum << "\n"; 489 NewSU = CreateClone(SU); 490 491 // New SUnit has the exact same predecessors. 492 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 493 I != E; ++I) 494 if (!I->isArtificial()) 495 AddPred(NewSU, *I); 496 497 // Only copy scheduled successors. Cut them from old node's successor 498 // list and move them over. 499 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; 500 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 501 I != E; ++I) { 502 if (I->isArtificial()) 503 continue; 504 SUnit *SuccSU = I->getSUnit(); 505 if (SuccSU->isScheduled) { 506 SDep D = *I; 507 D.setSUnit(NewSU); 508 AddPred(SuccSU, D); 509 D.setSUnit(SU); 510 DelDeps.push_back(std::make_pair(SuccSU, D)); 511 } 512 } 513 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) 514 RemovePred(DelDeps[i].first, DelDeps[i].second); 515 516 AvailableQueue->updateNode(SU); 517 AvailableQueue->addNode(NewSU); 518 519 ++NumDups; 520 return NewSU; 521} 522 523/// InsertCopiesAndMoveSuccs - Insert register copies and move all 524/// scheduled successors of the given SUnit to the last copy. 525void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, 526 const TargetRegisterClass *DestRC, 527 const TargetRegisterClass *SrcRC, 528 SmallVector<SUnit*, 2> &Copies) { 529 SUnit *CopyFromSU = CreateNewSUnit(NULL); 530 CopyFromSU->CopySrcRC = SrcRC; 531 CopyFromSU->CopyDstRC = DestRC; 532 533 SUnit *CopyToSU = CreateNewSUnit(NULL); 534 CopyToSU->CopySrcRC = DestRC; 535 CopyToSU->CopyDstRC = SrcRC; 536 537 // Only copy scheduled successors. Cut them from old node's successor 538 // list and move them over. 539 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; 540 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 541 I != E; ++I) { 542 if (I->isArtificial()) 543 continue; 544 SUnit *SuccSU = I->getSUnit(); 545 if (SuccSU->isScheduled) { 546 SDep D = *I; 547 D.setSUnit(CopyToSU); 548 AddPred(SuccSU, D); 549 DelDeps.push_back(std::make_pair(SuccSU, *I)); 550 } 551 } 552 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) 553 RemovePred(DelDeps[i].first, DelDeps[i].second); 554 555 AddPred(CopyFromSU, SDep(SU, SDep::Data, SU->Latency, Reg)); 556 AddPred(CopyToSU, SDep(CopyFromSU, SDep::Data, CopyFromSU->Latency, 0)); 557 558 AvailableQueue->updateNode(SU); 559 AvailableQueue->addNode(CopyFromSU); 560 AvailableQueue->addNode(CopyToSU); 561 Copies.push_back(CopyFromSU); 562 Copies.push_back(CopyToSU); 563 564 ++NumPRCopies; 565} 566 567/// getPhysicalRegisterVT - Returns the ValueType of the physical register 568/// definition of the specified node. 569/// FIXME: Move to SelectionDAG? 570static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, 571 const TargetInstrInfo *TII) { 572 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); 573 assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!"); 574 unsigned NumRes = TID.getNumDefs(); 575 for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) { 576 if (Reg == *ImpDef) 577 break; 578 ++NumRes; 579 } 580 return N->getValueType(NumRes); 581} 582 583/// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay 584/// scheduling of the given node to satisfy live physical register dependencies. 585/// If the specific node is the last one that's available to schedule, do 586/// whatever is necessary (i.e. backtracking or cloning) to make it possible. 587bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, 588 SmallVector<unsigned, 4> &LRegs){ 589 if (NumLiveRegs == 0) 590 return false; 591 592 SmallSet<unsigned, 4> RegAdded; 593 // If this node would clobber any "live" register, then it's not ready. 594 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 595 I != E; ++I) { 596 if (I->isAssignedRegDep()) { 597 unsigned Reg = I->getReg(); 598 if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != I->getSUnit()) { 599 if (RegAdded.insert(Reg)) 600 LRegs.push_back(Reg); 601 } 602 for (const unsigned *Alias = TRI->getAliasSet(Reg); 603 *Alias; ++Alias) 604 if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != I->getSUnit()) { 605 if (RegAdded.insert(*Alias)) 606 LRegs.push_back(*Alias); 607 } 608 } 609 } 610 611 for (SDNode *Node = SU->getNode(); Node; Node = Node->getFlaggedNode()) { 612 if (!Node->isMachineOpcode()) 613 continue; 614 const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode()); 615 if (!TID.ImplicitDefs) 616 continue; 617 for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) { 618 if (LiveRegDefs[*Reg] && LiveRegDefs[*Reg] != SU) { 619 if (RegAdded.insert(*Reg)) 620 LRegs.push_back(*Reg); 621 } 622 for (const unsigned *Alias = TRI->getAliasSet(*Reg); 623 *Alias; ++Alias) 624 if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != SU) { 625 if (RegAdded.insert(*Alias)) 626 LRegs.push_back(*Alias); 627 } 628 } 629 } 630 return !LRegs.empty(); 631} 632 633 634/// ListScheduleBottomUp - The main loop of list scheduling for bottom-up 635/// schedulers. 636void ScheduleDAGRRList::ListScheduleBottomUp() { 637 unsigned CurCycle = 0; 638 639 // Release any predecessors of the special Exit node. 640 ReleasePredecessors(&ExitSU, CurCycle); 641 642 // Add root to Available queue. 643 if (!SUnits.empty()) { 644 SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()]; 645 assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!"); 646 RootSU->isAvailable = true; 647 AvailableQueue->push(RootSU); 648 } 649 650 // While Available queue is not empty, grab the node with the highest 651 // priority. If it is not ready put it back. Schedule the node. 652 SmallVector<SUnit*, 4> NotReady; 653 DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMap; 654 Sequence.reserve(SUnits.size()); 655 while (!AvailableQueue->empty()) { 656 bool Delayed = false; 657 LRegsMap.clear(); 658 SUnit *CurSU = AvailableQueue->pop(); 659 while (CurSU) { 660 SmallVector<unsigned, 4> LRegs; 661 if (!DelayForLiveRegsBottomUp(CurSU, LRegs)) 662 break; 663 Delayed = true; 664 LRegsMap.insert(std::make_pair(CurSU, LRegs)); 665 666 CurSU->isPending = true; // This SU is not in AvailableQueue right now. 667 NotReady.push_back(CurSU); 668 CurSU = AvailableQueue->pop(); 669 } 670 671 // All candidates are delayed due to live physical reg dependencies. 672 // Try backtracking, code duplication, or inserting cross class copies 673 // to resolve it. 674 if (Delayed && !CurSU) { 675 for (unsigned i = 0, e = NotReady.size(); i != e; ++i) { 676 SUnit *TrySU = NotReady[i]; 677 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU]; 678 679 // Try unscheduling up to the point where it's safe to schedule 680 // this node. 681 unsigned LiveCycle = CurCycle; 682 for (unsigned j = 0, ee = LRegs.size(); j != ee; ++j) { 683 unsigned Reg = LRegs[j]; 684 unsigned LCycle = LiveRegCycles[Reg]; 685 LiveCycle = std::min(LiveCycle, LCycle); 686 } 687 SUnit *OldSU = Sequence[LiveCycle]; 688 if (!WillCreateCycle(TrySU, OldSU)) { 689 BacktrackBottomUp(TrySU, LiveCycle, CurCycle); 690 // Force the current node to be scheduled before the node that 691 // requires the physical reg dep. 692 if (OldSU->isAvailable) { 693 OldSU->isAvailable = false; 694 AvailableQueue->remove(OldSU); 695 } 696 AddPred(TrySU, SDep(OldSU, SDep::Order, /*Latency=*/1, 697 /*Reg=*/0, /*isNormalMemory=*/false, 698 /*isMustAlias=*/false, /*isArtificial=*/true)); 699 // If one or more successors has been unscheduled, then the current 700 // node is no longer avaialable. Schedule a successor that's now 701 // available instead. 702 if (!TrySU->isAvailable) 703 CurSU = AvailableQueue->pop(); 704 else { 705 CurSU = TrySU; 706 TrySU->isPending = false; 707 NotReady.erase(NotReady.begin()+i); 708 } 709 break; 710 } 711 } 712 713 if (!CurSU) { 714 // Can't backtrack. If it's too expensive to copy the value, then try 715 // duplicate the nodes that produces these "too expensive to copy" 716 // values to break the dependency. In case even that doesn't work, 717 // insert cross class copies. 718 // If it's not too expensive, i.e. cost != -1, issue copies. 719 SUnit *TrySU = NotReady[0]; 720 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU]; 721 assert(LRegs.size() == 1 && "Can't handle this yet!"); 722 unsigned Reg = LRegs[0]; 723 SUnit *LRDef = LiveRegDefs[Reg]; 724 MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII); 725 const TargetRegisterClass *RC = 726 TRI->getPhysicalRegisterRegClass(Reg, VT); 727 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); 728 729 // If cross copy register class is null, then it must be possible copy 730 // the value directly. Do not try duplicate the def. 731 SUnit *NewDef = 0; 732 if (DestRC) 733 NewDef = CopyAndMoveSuccessors(LRDef); 734 else 735 DestRC = RC; 736 if (!NewDef) { 737 // Issue copies, these can be expensive cross register class copies. 738 SmallVector<SUnit*, 2> Copies; 739 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); 740 DOUT << "Adding an edge from SU #" << TrySU->NodeNum 741 << " to SU #" << Copies.front()->NodeNum << "\n"; 742 AddPred(TrySU, SDep(Copies.front(), SDep::Order, /*Latency=*/1, 743 /*Reg=*/0, /*isNormalMemory=*/false, 744 /*isMustAlias=*/false, 745 /*isArtificial=*/true)); 746 NewDef = Copies.back(); 747 } 748 749 DOUT << "Adding an edge from SU #" << NewDef->NodeNum 750 << " to SU #" << TrySU->NodeNum << "\n"; 751 LiveRegDefs[Reg] = NewDef; 752 AddPred(NewDef, SDep(TrySU, SDep::Order, /*Latency=*/1, 753 /*Reg=*/0, /*isNormalMemory=*/false, 754 /*isMustAlias=*/false, 755 /*isArtificial=*/true)); 756 TrySU->isAvailable = false; 757 CurSU = NewDef; 758 } 759 760 assert(CurSU && "Unable to resolve live physical register dependencies!"); 761 } 762 763 // Add the nodes that aren't ready back onto the available list. 764 for (unsigned i = 0, e = NotReady.size(); i != e; ++i) { 765 NotReady[i]->isPending = false; 766 // May no longer be available due to backtracking. 767 if (NotReady[i]->isAvailable) 768 AvailableQueue->push(NotReady[i]); 769 } 770 NotReady.clear(); 771 772 if (CurSU) 773 ScheduleNodeBottomUp(CurSU, CurCycle); 774 ++CurCycle; 775 } 776 777 // Reverse the order if it is bottom up. 778 std::reverse(Sequence.begin(), Sequence.end()); 779 780#ifndef NDEBUG 781 VerifySchedule(isBottomUp); 782#endif 783} 784 785//===----------------------------------------------------------------------===// 786// Top-Down Scheduling 787//===----------------------------------------------------------------------===// 788 789/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to 790/// the AvailableQueue if the count reaches zero. Also update its cycle bound. 791void ScheduleDAGRRList::ReleaseSucc(SUnit *SU, const SDep *SuccEdge) { 792 SUnit *SuccSU = SuccEdge->getSUnit(); 793 --SuccSU->NumPredsLeft; 794 795#ifndef NDEBUG 796 if (SuccSU->NumPredsLeft < 0) { 797 cerr << "*** Scheduling failed! ***\n"; 798 SuccSU->dump(this); 799 cerr << " has been released too many times!\n"; 800 assert(0); 801 } 802#endif 803 804 // If all the node's predecessors are scheduled, this node is ready 805 // to be scheduled. Ignore the special ExitSU node. 806 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) { 807 SuccSU->isAvailable = true; 808 AvailableQueue->push(SuccSU); 809 } 810} 811 812void ScheduleDAGRRList::ReleaseSuccessors(SUnit *SU) { 813 // Top down: release successors 814 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 815 I != E; ++I) { 816 assert(!I->isAssignedRegDep() && 817 "The list-tdrr scheduler doesn't yet support physreg dependencies!"); 818 819 ReleaseSucc(SU, &*I); 820 } 821} 822 823/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending 824/// count of its successors. If a successor pending count is zero, add it to 825/// the Available queue. 826void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { 827 DOUT << "*** Scheduling [" << CurCycle << "]: "; 828 DEBUG(SU->dump(this)); 829 830 assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!"); 831 SU->setDepthToAtLeast(CurCycle); 832 Sequence.push_back(SU); 833 834 ReleaseSuccessors(SU); 835 SU->isScheduled = true; 836 AvailableQueue->ScheduledNode(SU); 837} 838 839/// ListScheduleTopDown - The main loop of list scheduling for top-down 840/// schedulers. 841void ScheduleDAGRRList::ListScheduleTopDown() { 842 unsigned CurCycle = 0; 843 844 // Release any successors of the special Entry node. 845 ReleaseSuccessors(&EntrySU); 846 847 // All leaves to Available queue. 848 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { 849 // It is available if it has no predecessors. 850 if (SUnits[i].Preds.empty()) { 851 AvailableQueue->push(&SUnits[i]); 852 SUnits[i].isAvailable = true; 853 } 854 } 855 856 // While Available queue is not empty, grab the node with the highest 857 // priority. If it is not ready put it back. Schedule the node. 858 Sequence.reserve(SUnits.size()); 859 while (!AvailableQueue->empty()) { 860 SUnit *CurSU = AvailableQueue->pop(); 861 862 if (CurSU) 863 ScheduleNodeTopDown(CurSU, CurCycle); 864 ++CurCycle; 865 } 866 867#ifndef NDEBUG 868 VerifySchedule(isBottomUp); 869#endif 870} 871 872 873//===----------------------------------------------------------------------===// 874// RegReductionPriorityQueue Implementation 875//===----------------------------------------------------------------------===// 876// 877// This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers 878// to reduce register pressure. 879// 880namespace { 881 template<class SF> 882 class RegReductionPriorityQueue; 883 884 /// Sorting functions for the Available queue. 885 struct bu_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> { 886 RegReductionPriorityQueue<bu_ls_rr_sort> *SPQ; 887 bu_ls_rr_sort(RegReductionPriorityQueue<bu_ls_rr_sort> *spq) : SPQ(spq) {} 888 bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {} 889 890 bool operator()(const SUnit* left, const SUnit* right) const; 891 }; 892 893 struct td_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> { 894 RegReductionPriorityQueue<td_ls_rr_sort> *SPQ; 895 td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {} 896 td_ls_rr_sort(const td_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {} 897 898 bool operator()(const SUnit* left, const SUnit* right) const; 899 }; 900} // end anonymous namespace 901 902/// CalcNodeSethiUllmanNumber - Compute Sethi Ullman number. 903/// Smaller number is the higher priority. 904static unsigned 905CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { 906 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum]; 907 if (SethiUllmanNumber != 0) 908 return SethiUllmanNumber; 909 910 unsigned Extra = 0; 911 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 912 I != E; ++I) { 913 if (I->isCtrl()) continue; // ignore chain preds 914 SUnit *PredSU = I->getSUnit(); 915 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU, SUNumbers); 916 if (PredSethiUllman > SethiUllmanNumber) { 917 SethiUllmanNumber = PredSethiUllman; 918 Extra = 0; 919 } else if (PredSethiUllman == SethiUllmanNumber) 920 ++Extra; 921 } 922 923 SethiUllmanNumber += Extra; 924 925 if (SethiUllmanNumber == 0) 926 SethiUllmanNumber = 1; 927 928 return SethiUllmanNumber; 929} 930 931namespace { 932 template<class SF> 933 class VISIBILITY_HIDDEN RegReductionPriorityQueue 934 : public SchedulingPriorityQueue { 935 PriorityQueue<SUnit*, std::vector<SUnit*>, SF> Queue; 936 unsigned currentQueueId; 937 938 protected: 939 // SUnits - The SUnits for the current graph. 940 std::vector<SUnit> *SUnits; 941 942 const TargetInstrInfo *TII; 943 const TargetRegisterInfo *TRI; 944 ScheduleDAGRRList *scheduleDAG; 945 946 // SethiUllmanNumbers - The SethiUllman number for each node. 947 std::vector<unsigned> SethiUllmanNumbers; 948 949 public: 950 RegReductionPriorityQueue(const TargetInstrInfo *tii, 951 const TargetRegisterInfo *tri) : 952 Queue(SF(this)), currentQueueId(0), 953 TII(tii), TRI(tri), scheduleDAG(NULL) {} 954 955 void initNodes(std::vector<SUnit> &sunits) { 956 SUnits = &sunits; 957 // Add pseudo dependency edges for two-address nodes. 958 AddPseudoTwoAddrDeps(); 959 // Calculate node priorities. 960 CalculateSethiUllmanNumbers(); 961 } 962 963 void addNode(const SUnit *SU) { 964 unsigned SUSize = SethiUllmanNumbers.size(); 965 if (SUnits->size() > SUSize) 966 SethiUllmanNumbers.resize(SUSize*2, 0); 967 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers); 968 } 969 970 void updateNode(const SUnit *SU) { 971 SethiUllmanNumbers[SU->NodeNum] = 0; 972 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers); 973 } 974 975 void releaseState() { 976 SUnits = 0; 977 SethiUllmanNumbers.clear(); 978 } 979 980 unsigned getNodePriority(const SUnit *SU) const { 981 assert(SU->NodeNum < SethiUllmanNumbers.size()); 982 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0; 983 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) 984 // CopyToReg should be close to its uses to facilitate coalescing and 985 // avoid spilling. 986 return 0; 987 if (Opc == TargetInstrInfo::EXTRACT_SUBREG || 988 Opc == TargetInstrInfo::INSERT_SUBREG) 989 // EXTRACT_SUBREG / INSERT_SUBREG should be close to its use to 990 // facilitate coalescing. 991 return 0; 992 if (SU->NumSuccs == 0 && SU->NumPreds != 0) 993 // If SU does not have a register use, i.e. it doesn't produce a value 994 // that would be consumed (e.g. store), then it terminates a chain of 995 // computation. Give it a large SethiUllman number so it will be 996 // scheduled right before its predecessors that it doesn't lengthen 997 // their live ranges. 998 return 0xffff; 999 if (SU->NumPreds == 0 && SU->NumSuccs != 0) 1000 // If SU does not have a register def, schedule it close to its uses 1001 // because it does not lengthen any live ranges. 1002 return 0; 1003 return SethiUllmanNumbers[SU->NodeNum]; 1004 } 1005 1006 unsigned size() const { return Queue.size(); } 1007 1008 bool empty() const { return Queue.empty(); } 1009 1010 void push(SUnit *U) { 1011 assert(!U->NodeQueueId && "Node in the queue already"); 1012 U->NodeQueueId = ++currentQueueId; 1013 Queue.push(U); 1014 } 1015 1016 void push_all(const std::vector<SUnit *> &Nodes) { 1017 for (unsigned i = 0, e = Nodes.size(); i != e; ++i) 1018 push(Nodes[i]); 1019 } 1020 1021 SUnit *pop() { 1022 if (empty()) return NULL; 1023 SUnit *V = Queue.top(); 1024 Queue.pop(); 1025 V->NodeQueueId = 0; 1026 return V; 1027 } 1028 1029 void remove(SUnit *SU) { 1030 assert(!Queue.empty() && "Queue is empty!"); 1031 assert(SU->NodeQueueId != 0 && "Not in queue!"); 1032 Queue.erase_one(SU); 1033 SU->NodeQueueId = 0; 1034 } 1035 1036 void setScheduleDAG(ScheduleDAGRRList *scheduleDag) { 1037 scheduleDAG = scheduleDag; 1038 } 1039 1040 protected: 1041 bool canClobber(const SUnit *SU, const SUnit *Op); 1042 void AddPseudoTwoAddrDeps(); 1043 void CalculateSethiUllmanNumbers(); 1044 }; 1045 1046 typedef RegReductionPriorityQueue<bu_ls_rr_sort> 1047 BURegReductionPriorityQueue; 1048 1049 typedef RegReductionPriorityQueue<td_ls_rr_sort> 1050 TDRegReductionPriorityQueue; 1051} 1052 1053/// closestSucc - Returns the scheduled cycle of the successor which is 1054/// closet to the current cycle. 1055static unsigned closestSucc(const SUnit *SU) { 1056 unsigned MaxHeight = 0; 1057 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 1058 I != E; ++I) { 1059 if (I->isCtrl()) continue; // ignore chain succs 1060 unsigned Height = I->getSUnit()->getHeight(); 1061 // If there are bunch of CopyToRegs stacked up, they should be considered 1062 // to be at the same position. 1063 if (I->getSUnit()->getNode() && 1064 I->getSUnit()->getNode()->getOpcode() == ISD::CopyToReg) 1065 Height = closestSucc(I->getSUnit())+1; 1066 if (Height > MaxHeight) 1067 MaxHeight = Height; 1068 } 1069 return MaxHeight; 1070} 1071 1072/// calcMaxScratches - Returns an cost estimate of the worse case requirement 1073/// for scratch registers, i.e. number of data dependencies. 1074static unsigned calcMaxScratches(const SUnit *SU) { 1075 unsigned Scratches = 0; 1076 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 1077 I != E; ++I) { 1078 if (I->isCtrl()) continue; // ignore chain preds 1079 Scratches++; 1080 } 1081 return Scratches; 1082} 1083 1084// Bottom up 1085bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { 1086 unsigned LPriority = SPQ->getNodePriority(left); 1087 unsigned RPriority = SPQ->getNodePriority(right); 1088 if (LPriority != RPriority) 1089 return LPriority > RPriority; 1090 1091 // Try schedule def + use closer when Sethi-Ullman numbers are the same. 1092 // e.g. 1093 // t1 = op t2, c1 1094 // t3 = op t4, c2 1095 // 1096 // and the following instructions are both ready. 1097 // t2 = op c3 1098 // t4 = op c4 1099 // 1100 // Then schedule t2 = op first. 1101 // i.e. 1102 // t4 = op c4 1103 // t2 = op c3 1104 // t1 = op t2, c1 1105 // t3 = op t4, c2 1106 // 1107 // This creates more short live intervals. 1108 unsigned LDist = closestSucc(left); 1109 unsigned RDist = closestSucc(right); 1110 if (LDist != RDist) 1111 return LDist < RDist; 1112 1113 // How many registers becomes live when the node is scheduled. 1114 unsigned LScratch = calcMaxScratches(left); 1115 unsigned RScratch = calcMaxScratches(right); 1116 if (LScratch != RScratch) 1117 return LScratch > RScratch; 1118 1119 if (left->getHeight() != right->getHeight()) 1120 return left->getHeight() > right->getHeight(); 1121 1122 if (left->getDepth() != right->getDepth()) 1123 return left->getDepth() < right->getDepth(); 1124 1125 assert(left->NodeQueueId && right->NodeQueueId && 1126 "NodeQueueId cannot be zero"); 1127 return (left->NodeQueueId > right->NodeQueueId); 1128} 1129 1130template<class SF> 1131bool 1132RegReductionPriorityQueue<SF>::canClobber(const SUnit *SU, const SUnit *Op) { 1133 if (SU->isTwoAddress) { 1134 unsigned Opc = SU->getNode()->getMachineOpcode(); 1135 const TargetInstrDesc &TID = TII->get(Opc); 1136 unsigned NumRes = TID.getNumDefs(); 1137 unsigned NumOps = TID.getNumOperands() - NumRes; 1138 for (unsigned i = 0; i != NumOps; ++i) { 1139 if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) { 1140 SDNode *DU = SU->getNode()->getOperand(i).getNode(); 1141 if (DU->getNodeId() != -1 && 1142 Op->OrigNode == &(*SUnits)[DU->getNodeId()]) 1143 return true; 1144 } 1145 } 1146 } 1147 return false; 1148} 1149 1150 1151/// hasCopyToRegUse - Return true if SU has a value successor that is a 1152/// CopyToReg node. 1153static bool hasCopyToRegUse(const SUnit *SU) { 1154 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 1155 I != E; ++I) { 1156 if (I->isCtrl()) continue; 1157 const SUnit *SuccSU = I->getSUnit(); 1158 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) 1159 return true; 1160 } 1161 return false; 1162} 1163 1164/// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's 1165/// physical register defs. 1166static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU, 1167 const TargetInstrInfo *TII, 1168 const TargetRegisterInfo *TRI) { 1169 SDNode *N = SuccSU->getNode(); 1170 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); 1171 const unsigned *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs(); 1172 assert(ImpDefs && "Caller should check hasPhysRegDefs"); 1173 const unsigned *SUImpDefs = 1174 TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs(); 1175 if (!SUImpDefs) 1176 return false; 1177 for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) { 1178 MVT VT = N->getValueType(i); 1179 if (VT == MVT::Flag || VT == MVT::Other) 1180 continue; 1181 if (!N->hasAnyUseOfValue(i)) 1182 continue; 1183 unsigned Reg = ImpDefs[i - NumDefs]; 1184 for (;*SUImpDefs; ++SUImpDefs) { 1185 unsigned SUReg = *SUImpDefs; 1186 if (TRI->regsOverlap(Reg, SUReg)) 1187 return true; 1188 } 1189 } 1190 return false; 1191} 1192 1193/// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses 1194/// it as a def&use operand. Add a pseudo control edge from it to the other 1195/// node (if it won't create a cycle) so the two-address one will be scheduled 1196/// first (lower in the schedule). If both nodes are two-address, favor the 1197/// one that has a CopyToReg use (more likely to be a loop induction update). 1198/// If both are two-address, but one is commutable while the other is not 1199/// commutable, favor the one that's not commutable. 1200template<class SF> 1201void RegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() { 1202 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) { 1203 SUnit *SU = &(*SUnits)[i]; 1204 if (!SU->isTwoAddress) 1205 continue; 1206 1207 SDNode *Node = SU->getNode(); 1208 if (!Node || !Node->isMachineOpcode() || SU->getNode()->getFlaggedNode()) 1209 continue; 1210 1211 unsigned Opc = Node->getMachineOpcode(); 1212 const TargetInstrDesc &TID = TII->get(Opc); 1213 unsigned NumRes = TID.getNumDefs(); 1214 unsigned NumOps = TID.getNumOperands() - NumRes; 1215 for (unsigned j = 0; j != NumOps; ++j) { 1216 if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1) 1217 continue; 1218 SDNode *DU = SU->getNode()->getOperand(j).getNode(); 1219 if (DU->getNodeId() == -1) 1220 continue; 1221 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()]; 1222 if (!DUSU) continue; 1223 for (SUnit::const_succ_iterator I = DUSU->Succs.begin(), 1224 E = DUSU->Succs.end(); I != E; ++I) { 1225 if (I->isCtrl()) continue; 1226 SUnit *SuccSU = I->getSUnit(); 1227 if (SuccSU == SU) 1228 continue; 1229 // Be conservative. Ignore if nodes aren't at roughly the same 1230 // depth and height. 1231 if (SuccSU->getHeight() < SU->getHeight() && 1232 (SU->getHeight() - SuccSU->getHeight()) > 1) 1233 continue; 1234 if (!SuccSU->getNode() || !SuccSU->getNode()->isMachineOpcode()) 1235 continue; 1236 // Don't constrain nodes with physical register defs if the 1237 // predecessor can clobber them. 1238 if (SuccSU->hasPhysRegDefs) { 1239 if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI)) 1240 continue; 1241 } 1242 // Don't constrain extract_subreg / insert_subreg; these may be 1243 // coalesced away. We want them close to their uses. 1244 unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode(); 1245 if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG || 1246 SuccOpc == TargetInstrInfo::INSERT_SUBREG) 1247 continue; 1248 if ((!canClobber(SuccSU, DUSU) || 1249 (hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) || 1250 (!SU->isCommutable && SuccSU->isCommutable)) && 1251 !scheduleDAG->IsReachable(SuccSU, SU)) { 1252 DOUT << "Adding a pseudo-two-addr edge from SU # " << SU->NodeNum 1253 << " to SU #" << SuccSU->NodeNum << "\n"; 1254 scheduleDAG->AddPred(SU, SDep(SuccSU, SDep::Order, /*Latency=*/0, 1255 /*Reg=*/0, /*isNormalMemory=*/false, 1256 /*isMustAlias=*/false, 1257 /*isArtificial=*/true)); 1258 } 1259 } 1260 } 1261 } 1262} 1263 1264/// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all 1265/// scheduling units. 1266template<class SF> 1267void RegReductionPriorityQueue<SF>::CalculateSethiUllmanNumbers() { 1268 SethiUllmanNumbers.assign(SUnits->size(), 0); 1269 1270 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) 1271 CalcNodeSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers); 1272} 1273 1274/// LimitedSumOfUnscheduledPredsOfSuccs - Compute the sum of the unscheduled 1275/// predecessors of the successors of the SUnit SU. Stop when the provided 1276/// limit is exceeded. 1277static unsigned LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU, 1278 unsigned Limit) { 1279 unsigned Sum = 0; 1280 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 1281 I != E; ++I) { 1282 const SUnit *SuccSU = I->getSUnit(); 1283 for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(), 1284 EE = SuccSU->Preds.end(); II != EE; ++II) { 1285 SUnit *PredSU = II->getSUnit(); 1286 if (!PredSU->isScheduled) 1287 if (++Sum > Limit) 1288 return Sum; 1289 } 1290 } 1291 return Sum; 1292} 1293 1294 1295// Top down 1296bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { 1297 unsigned LPriority = SPQ->getNodePriority(left); 1298 unsigned RPriority = SPQ->getNodePriority(right); 1299 bool LIsTarget = left->getNode() && left->getNode()->isMachineOpcode(); 1300 bool RIsTarget = right->getNode() && right->getNode()->isMachineOpcode(); 1301 bool LIsFloater = LIsTarget && left->NumPreds == 0; 1302 bool RIsFloater = RIsTarget && right->NumPreds == 0; 1303 unsigned LBonus = (LimitedSumOfUnscheduledPredsOfSuccs(left,1) == 1) ? 2 : 0; 1304 unsigned RBonus = (LimitedSumOfUnscheduledPredsOfSuccs(right,1) == 1) ? 2 : 0; 1305 1306 if (left->NumSuccs == 0 && right->NumSuccs != 0) 1307 return false; 1308 else if (left->NumSuccs != 0 && right->NumSuccs == 0) 1309 return true; 1310 1311 if (LIsFloater) 1312 LBonus -= 2; 1313 if (RIsFloater) 1314 RBonus -= 2; 1315 if (left->NumSuccs == 1) 1316 LBonus += 2; 1317 if (right->NumSuccs == 1) 1318 RBonus += 2; 1319 1320 if (LPriority+LBonus != RPriority+RBonus) 1321 return LPriority+LBonus < RPriority+RBonus; 1322 1323 if (left->getDepth() != right->getDepth()) 1324 return left->getDepth() < right->getDepth(); 1325 1326 if (left->NumSuccsLeft != right->NumSuccsLeft) 1327 return left->NumSuccsLeft > right->NumSuccsLeft; 1328 1329 assert(left->NodeQueueId && right->NodeQueueId && 1330 "NodeQueueId cannot be zero"); 1331 return (left->NodeQueueId > right->NodeQueueId); 1332} 1333 1334//===----------------------------------------------------------------------===// 1335// Public Constructor Functions 1336//===----------------------------------------------------------------------===// 1337 1338llvm::ScheduleDAGSDNodes * 1339llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) { 1340 const TargetMachine &TM = IS->TM; 1341 const TargetInstrInfo *TII = TM.getInstrInfo(); 1342 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); 1343 1344 BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI); 1345 1346 ScheduleDAGRRList *SD = 1347 new ScheduleDAGRRList(*IS->MF, true, PQ); 1348 PQ->setScheduleDAG(SD); 1349 return SD; 1350} 1351 1352llvm::ScheduleDAGSDNodes * 1353llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) { 1354 const TargetMachine &TM = IS->TM; 1355 const TargetInstrInfo *TII = TM.getInstrInfo(); 1356 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); 1357 1358 TDRegReductionPriorityQueue *PQ = new TDRegReductionPriorityQueue(TII, TRI); 1359 1360 ScheduleDAGRRList *SD = 1361 new ScheduleDAGRRList(*IS->MF, false, PQ); 1362 PQ->setScheduleDAG(SD); 1363 return SD; 1364} 1365