Searched defs:RegClassInfo (Results 1 - 8 of 8) sorted by relevance

/external/llvm/lib/CodeGen/
H A DAllocationOrder.cpp32 const RegisterClassInfo &RegClassInfo)
36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
30 AllocationOrder(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo) argument
H A DCriticalAntiDepBreaker.h39 const RegisterClassInfo &RegClassInfo; member in class:llvm::CriticalAntiDepBreaker
H A DRegAllocBase.h66 RegisterClassInfo RegClassInfo; member in class:llvm::RegAllocBase
H A DAggressiveAntiDepBreaker.h122 const RegisterClassInfo &RegClassInfo; member in class:llvm::AggressiveAntiDepBreaker
H A DPostRASchedulerList.cpp83 RegisterClassInfo RegClassInfo; member in class:__anon25784::PostRAScheduler
258 RegClassInfo.runOnMachineFunction(Fn);
287 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
H A DRegAllocFast.cpp61 RegisterClassInfo RegClassInfo; member in class:__anon25790::RAFast
536 ArrayRef<MCPhysReg> AO = RegClassInfo.getOrder(RC);
1077 RegClassInfo.runOnMachineFunction(Fn);
H A DRegisterCoalescer.cpp87 RegisterClassInfo RegClassInfo; member in class:__anon25794::RegisterCoalescer
1152 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
2234 RegClassInfo.runOnMachineFunction(fn);
/external/llvm/include/llvm/CodeGen/
H A DMachineScheduler.h110 RegisterClassInfo *RegClassInfo; member in struct:llvm::MachineSchedContext
349 RegisterClassInfo *RegClassInfo; member in class:llvm::ScheduleDAGMILive
385 RegClassInfo(C->RegClassInfo), DFSResult(nullptr),

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