| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 81f69410cb942079964481aba8d1c4739b77290f |
|
16-Oct-2013 |
Andrew Trick <atrick@apple.com> |
After PostRA scheduling, don't set kill flags on undef operands.
This should fix the ATOM buildbot failing on break-avx-dep.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192824 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| d2763f6ce62eaa497e944331668414e35f3712f3 |
|
23-Aug-2013 |
Andrew Trick <atrick@apple.com> |
mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr count.
This fixes a pathological compile time problem with very large blocks
and lots of scheduling boundaries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189116 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 62c320a755ac27ac2b7f64e927892249e0f486e0 |
|
23-May-2013 |
Chad Rosier <mcrosier@apple.com> |
Simplify logic now that r182490 is in place. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| b45e4deb102d47602f5b941da7f412ecc9a867e9 |
|
05-Feb-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove special-casing of return blocks for liveness.
Now that return value registers are return instruction uses, there is no
need for special treatment of return blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174416 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 7b79b9862c9e6fc31ec072acb09171fd6ec7b0e0 |
|
20-Dec-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use MachineInstrBuilder in a few CodeGen passes.
This automatically passes a context pointer to MI->addOperand().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| cf6b6131dd0da37903a6e3a5173ea12aa8263713 |
|
13-Nov-2012 |
Andrew Trick <atrick@apple.com> |
misched: Don't consider artificial edges weak edges.
For now be more conservative in case other out-of-tree schedulers rely
on the old behavior of artificial edges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167808 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| ae692f2baedf53504af2715993b166950e185a55 |
|
12-Nov-2012 |
Andrew Trick <atrick@apple.com> |
misched: Infrastructure for weak DAG edges.
This adds support for weak DAG edges to the general scheduling
infrastructure in preparation for MachineScheduler support for
heuristics based on weak edges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| fb9ebbf236974beac31705eaeb9f50ab585af6ab |
|
15-Oct-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch most getReservedRegs() clients to the MRI equivalent.
Using the cached bit vector in MRI avoids comstantly allocating and
recomputing the reserved register bit vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165983 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| b720be6a50f4e1b3280d2b029ee38dda14577525 |
|
12-Sep-2012 |
Manman Ren <mren@apple.com> |
Release build: guard dump functions with
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)"
No functional change. Update r163339.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 77e300e8f0b8db8eec448cae9c87d7c5bfad9757 |
|
06-Sep-2012 |
Manman Ren <mren@apple.com> |
Release build: guard dump functions with "ifndef NDEBUG"
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 96601ca332ab388754ca4673be8973396fea2ddd |
|
22-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162347 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 1525260b3e50cc578939ef41b60609689eecfdd2 |
|
06-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Move RegisterClassInfo.h.
Allow targets to access this API. It's required for RegisterPressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| a7542d5f870c5d98960d1676e23ac1d1d975d7e5 |
|
06-Jun-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove unused private fields found by clang's new -Wunused-private-field.
There are some that I didn't remove this round because they looked like
obvious stubs. There are dead variables in gtest too, they should be
fixed upstream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 396618b43a85e12d290a90b181c6af5d7c0c5f11 |
|
02-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch all register list clients to the new MC*Iterator interface.
No functional change intended.
Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.
This makes it possible to do so without changing all clients (again).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 6a8c7bf8e72338e55f0f9583e1828f62da165d4a |
|
23-Apr-2012 |
Preston Gurd <preston.gurd@intel.com> |
This patch fixes a problem which arose when using the Post-RA scheduler
on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks which did not
contain live-in information. When the anti-dependency code in the Post-RA
scheduler ran, it would sometimes rename the register containing
the function return value because the fact that the return value was
live-in to the subsequent block had been lost. To fix this, it is necessary
to run the RegisterScavenging code in the BranchFolding pass.
This patch makes sure that the register scavenging code is invoked
in the X86 subtarget only when post-RA scheduling is being done.
Post RA scheduling in the X86 subtarget is only done for Atom.
This patch adds a new function to the TargetRegisterClass to control
whether or not live-ins should be preserved during branch folding.
This is necessary in order for the anti-dependency optimizations done
during the PostRASchedulerList pass to work properly when doing
Post-RA scheduling for the X86 in general and for the Intel Atom in particular.
The patch adds and invokes the new function trackLivenessAfterRegAlloc()
instead of using the existing requiresRegisterScavenging().
It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of
requiresRegisterScavenging(). It changes the all the targets that
implemented requiresRegisterScavenging() to also implement
trackLivenessAfterRegAlloc().
It adds an assertion in the Post RA scheduler to make sure that post RA
liveness information is available when it is needed.
It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order
to avoid running into the added assertion.
Finally, this patch restores the use of anti-dependency checking
(which was turned off temporarily for the 3.1 release) for
Intel Atom in the Post RA scheduler.
Patch by Andy Zhang!
Thanks to Jakob and Anton for their reviews.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 68675c6c5b173021807e4e12cd250eeba63f6d0d |
|
09-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched interface: rename Begin/End to RegionBegin/RegionEnd since they are not private.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| ed395c8c475692f5a43eb4b5c5562503d67616d0 |
|
08-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched prep: Expose the ScheduleDAGInstrs interface so targets may
implement their own MachineScheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| cf46b5acfd6e0ab5d21ec3160cec195d0eb77b0b |
|
08-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched prep: rename InsertPos to End.
ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152256 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 953be893e8cffa0ef9bf410036cd96aeb526e98a |
|
08-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: rename core scheduler methods for consistency.
We had half the API with one convention, half with another. Now was a
good time to clean it up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 47c144505b9be28ed22c626b3a407c11dba2fec5 |
|
07-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.
ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation.
ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class.
ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target.
Specific changes:
- Removed driver code from ScheduleDAG. clearDAG is the only interface needed.
- Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls.
- Added ScheduleDAGInstrs::begin()/end() public API.
- Moved Sequence into the driver layer, which is specific to the scheduling algorithm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 84b454d1a270a5d685e01686ed15e68c44b0b56a |
|
07-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: modularize schedule emission.
ScheduleDAG has nothing to do with how the instructions are scheduled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 73ba69b6843f7f23345b1e8745cb328952cae0d8 |
|
07-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: modularize schedule printing.
ScheduleDAG will not refer to the scheduled instruction sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152205 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 4c727204271067f3dbf50bd23098b2df8e1cc47a |
|
07-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: modularize schedule verification.
ScheduleDAG will not refer to the scheduled instruction sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 9ebfbf8b9fd5f982e0db9293808bd32168615ba9 |
|
05-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| b6bd8ccd02f7c2febee19b1eae2cb1ce90ad4001 |
|
23-Feb-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
BitVectorize loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 46252d8ea1d264ca341e3ca3e7f4e3c82e32940e |
|
23-Feb-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
post-ra-sched: Turn the KillIndices vector into a bitvector, it only stored two meaningful states.
Rename it to LiveRegs to make it more clear what's stored inside.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 49b726c339b6f3b9c51638bd0f453610f9765f2d |
|
23-Feb-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
post-ra-sched: Replace a std::set of regs with a bitvector.
Assuming that a single std::set node adds 3 control words, a bitvector
can store (3*8+4)*8=224 registers in the allocated memory of a single
element in the std::set (x86_64). Also we don't have to call malloc
for every register added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151269 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 976647d95da89e38c66d9ed869a9d345b36d386d |
|
23-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Make calls scheduling boundaries post-ra.
Before register allocation, instructions can be moved across calls in
order to reduce register pressure. After register allocation, we don't
gain a lot by moving callee-saved defs across calls. In fact, since the
scheduler doesn't have a good idea how registers are used in the callee,
it can't really make good scheduling decisions.
This changes the schedule in two ways: 1. Latencies to call uses and
defs are no longer accounted for, causing some random shuffling around
calls. This isn't really a problem since those uses and defs are
inaccurate proxies for what happens inside the callee. They don't
represent registers used by the call instruction itself.
2. Instructions are no longer moved across calls. This didn't happen
very often, and the scheduling decision was made on dubious information
anyway.
As with any scheduling change, benchmark numbers shift around a bit,
but there is no positive or negative trend from this change.
This makes the post-ra scheduler 5% faster for ARM targets.
The secret motivation for this patch is the introduction of register
mask operands representing call clobbers. The most efficient way of
handling regmasks in ScheduleDAGInstrs is to model them as barriers for
physreg live ranges, but not for virtreg live ranges. That's fine
pre-ra, but post-ra it would have the same effect as this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151265 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| f19a5926cb1fcd145a61116b7dd2b18312e76fd7 |
|
23-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle regmasks in FixupKills.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 44d23825d61d530b8d562329ec8fc2d4f843bb8d |
|
22-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 1dd8c8560d45d36a8e507cd014352f1d313f9f9e |
|
08-Feb-2012 |
Andrew Trick <atrick@apple.com> |
Codegen pass definition cleanup. No functionality.
Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.
Use INITIALIZE_PASS consistently.
Add a call to the initializer from CodeGen.cpp.
Remove redundant "createPass" functions and "getPassName" methods.
While cleaning up declarations, cleaned up comments (sorry for large diff).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150100 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| c7d081b5946b9ff9f7400d5b41f36cad3fc317aa |
|
08-Feb-2012 |
Andrew Trick <atrick@apple.com> |
Move pass configuration out of pass constructors: PostRAScheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 5e920d7c83c20474fc3470209869978628ccf8da |
|
14-Jan-2012 |
Andrew Trick <atrick@apple.com> |
misched: Added ScheduleDAGInstrs::IsPostRA
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| ddfd1377d2e4154d44dc3ad217735adc15af2e3f |
|
14-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 5a96b3dad2f634c9081c8b2b6c2575441dc5a2bd |
|
07-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| a7b0cb759433c715065440ee2a963a04db7f2b0b |
|
15-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove all remaining uses of Value::getNameStr().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144648 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 5b1b4489cf3a0f56f8be0673fc5cc380a32d277b |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetSubtarget to TargetSubtargetInfo for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| fa796dd720f1b34596a043f17f098fac18ecc028 |
|
16-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Teach antidependency breakers to use RegisterClassInfo.
No functional change was intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133202 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| e29e8e100ea38be1771e5f010a5511cbb990d515 |
|
02-Jun-2011 |
Devang Patel <dpatel@apple.com> |
Update DBG_VALUEs while breaking anti dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132487 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| cf9aa284b332bc2613def3612b80c5883d4b9985 |
|
01-Jun-2011 |
Andrew Trick <atrick@apple.com> |
Add an issue width check to the postRA scheduler. Patch by Max Kazakov!
For targets with no itinerary (x86) it is a nop by default. For
targets with issue width already expressed in the itinerary (ARM) it
bypasses a scoreboard check but otherwise does not affect the
schedule. It does make the code more consistent and complete and
allows new targets to specify their issue width in an arbitrary way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132385 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 89fd43778e47b0698582f906e3dac900c376102e |
|
06-May-2011 |
Andrew Trick <atrick@apple.com> |
Typo: Reviewed by Alistair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 15ab3594eba495ffd1f070207a4aceeae9492c11 |
|
06-May-2011 |
Andrew Trick <atrick@apple.com> |
Post-RA scheduler compile time fix. Quadratic computation of DAG node depth.
The post-ra scheduler was explicitly updating the depth of a node's
successors after scheduling it, regardless of whether the successor
was ready. This is quadratic for DAGs with transitively redundant
edges. I simply removed the useless update of depth, which is lazilly
computed later.
Fixes <rdar://problem/9044332> compiler takes way too long to build TextInput.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130992 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 2da8bc8a5f7705ac131184cd247f48500da0d74e |
|
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 |
|
10-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 90c579de5a383cee278acc3f7e7b9d0a656e6a35 |
|
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Reapply r110396, with fixes to appease the Linux buildbot gods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 1f74590e9d1b9cf0f1f81a156efea73f76546e05 |
|
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Revert r110396 to fix buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 9ccaf53ada99c63737547c0235baeb8454b04e80 |
|
06-Aug-2010 |
Owen Anderson <resistor@mac.com> |
Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier. Clean up APIs related to this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 24173da61db2725bf91b0edf57cfa554ac105e9d |
|
15-Jul-2010 |
Bill Wendling <isanbard@gmail.com> |
Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 86050dc8cc0aaea8c9dfeb89de02cafbd7f48d92 |
|
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 774bc882fdb3bbb0558075360c6e5bc510a0bdad |
|
14-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Do away with SimpleHazardRecognizer.h. It's not used and offers little value.
- Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 729aab3dd3a6ea5ca23430936270154090fcc10b |
|
12-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow target to provide its own hazard recognizer to post-ra scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 1015ba7018c87f48cc7bb45a564eb4a27241e76a |
|
21-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 76526f88632325fab1c33d9c1a8248087eb5e548 |
|
20-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove dbg_value workaround and associated command line option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104254 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| de70b1f9be3a483064e4696fac5a7d41ebe19140 |
|
20-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Enable preserving debug information through post-RA scheduling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 9001303a3fc3e901c1e5e8b5daea56e55989c114 |
|
14-May-2010 |
Jim Grosbach <grosbach@apple.com> |
80 column and trailing whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 5468e0928bcbfc18890d32c7525d281c14e6c303 |
|
14-May-2010 |
Jim Grosbach <grosbach@apple.com> |
add cmd line option to leave dbgvalues in during post-RA sceduling. Useful
while debugging what's mishandled about them in the post-RA pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103805 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| af1d8ca44a18f304f207e209b3bdb94b590f86ff |
|
01-May-2010 |
Dan Gohman <gohman@apple.com> |
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 8295d4c96c8530acb7ae0098d813b53dc4fe0a89 |
|
17-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
As a temporary workaround for post-RA not handling DebugValue instructions,
just remove them all. Radar 7873207 (working around the root problem of
Radar 7759363).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 8b3d6682a45e80d08abf32aa1be0491db1977456 |
|
12-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Remove a #include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| b0812f114b83a32c4b90a4b553c7177c557558b5 |
|
05-Mar-2010 |
Dale Johannesen <dalej@apple.com> |
Fix some more places where dbg_value affected codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97765 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| e1b2129471e994cfb7d34cc5134eb99dd1ae39f2 |
|
05-Jan-2010 |
David Greene <greened@obbligato.org> |
Change errs() to dbgs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 990d2857654cb80e46d207533834be3047494830 |
|
09-Dec-2009 |
David Goodwin <david_goodwin@apple.com> |
<rdar://problem/7453528>. Track only physical registers that are valid for the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90970 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 15d75d9f11f877bf3716257013b563e67341b0ed |
|
03-Dec-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't hang on to pointers or references after vector::push_back.
The MO reference to a MachineOperand can be invalidated by
MachineInstr::addOperand. Don't even use it for debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 557bbe6b5d13faaec38f85a266db457c7cb09ff2 |
|
20-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 87d21b92fc42f6b3bd8567a83fc5b5191c1205e5 |
|
13-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow target to specify regclass for which antideps will only be broken along the critical path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 12dd99dc308150a6beff32aafc824e1d6fec1139 |
|
12-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Rename registers to break output dependencies in addition to anti-dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87015 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| c2e8a7e8d2ab156afaa8ab0d0317dd9ee3db7d30 |
|
10-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Fixed to address code review. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 0855dee564f80160abf95497475306af38ab7f84 |
|
10-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 54097836f31660bd5e84c34ee8c92d237844315f |
|
05-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Break anti-dependencies using free registers in a round-robin manner to avoid introducing new anti-dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 4de099d8ca651e00fa5fac22bace4f4dba2d0292 |
|
03-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 0ba90f3e34b826b039bdfece1415ef032c4ad3f5 |
|
31-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Make -print-machineinstrs more readable.
- Be consistent when referring to MachineBasicBlocks: BB#0.
- Be consistent when referring to virtual registers: %reg1024.
- Be consistent when referring to unknown physical registers: %physreg10.
- Be consistent when referring to known physical registers: %RAX
- Be consistent when referring to register 0: %reg0
- Be consistent when printing alignments: align=16
- Print jump table contents.
- Don't print host addresses, in general.
- and various other cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 82c7248518a8b759a567fbb4b3176542ad2cf414 |
|
28-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Make AntiDepReg.h internal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85412 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| e10deca33e74a7c70ab585f78eee3fb52937f668 |
|
26-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow the aggressive anti-dep breaker to process the same region multiple times. This is necessary because new anti-dependencies are exposed when "current" ones are broken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85166 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| ada0ef86d98df4ac36808e4a0f0098250bf1a842 |
|
26-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Define virtual destructor in *.cpp file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 348777110a960f0e017025dd5141cb29472c3984 |
|
26-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Add aggressive anti-dependence breaker. Currently it is not the default for any target. Enable with -break-anti-dependencies=all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85145 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 2e7be612d5d0eb42ee3ae08194dbb03b750cc6bf |
|
26-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Break anti-dependence breaking out into its own class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| f5a86f45e75ec744c203270ffa03659eb0a220c1 |
|
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 6726b6d75a8b679068a58cb954ba97cf9d1690ba |
|
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 4c3715c2e5e17d7216a96ac2baf9720630f04408 |
|
23-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| c1ae8c9b8f426b74215abf0f7e46bffecc6f52d9 |
|
21-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Revert r84658 and r84691. They were causing llvm-gcc bootstrap to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 7441d14873cca4af68a0347d41676c476e0ab1f5 |
|
21-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Respect src register allocation requirements when breaking anti-dependencies. Remove some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 480c529e026942f28e1a792d2cec6d6b5bc0edba |
|
20-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint more aggressive anti-dependency breaking for post-ra scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84658 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| fa16354e0370fe884830286923352268b036737d |
|
16-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change createPostRAScheduler so it can be turned off at llc -O1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| c83da2f9e389332b9cf8eae9d823f745be5624b8 |
|
16-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
If post-alloc scheduler is not enabled, it should return false, not true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84248 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| d452ea6a6417e4ce7e110249c5e74bcc6ab1ae49 |
|
13-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Add debugging output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 5bf7c2a34679b6afe46ba4f605f1921da950a66b |
|
10-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Fix a missing initialization of PostRAScheduler's AA member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| a70dca156fa76d452f54829b5c5f962ddfd94ef2 |
|
10-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Factor out LiveIntervalAnalysis' code to determine whether an instruction
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.
This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 8bff4af61219031345e7dae0c1840315e6bfab7f |
|
02-Oct-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix a use-after-free in post-ra-scheduling.
MI->addOperand invalidates references to it's operands, avoid touching
the operand after a new one was added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83249 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 63bcbb72f75c92e3eff4d994eb1e8cb6d64c6e9b |
|
02-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
All callee-saved registers are live-out of a return block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 9843a93e830e76f96e9a997b3002624a28ca5aa6 |
|
02-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 471850ab84301dd47cab2bf8d694fcb5766c1169 |
|
01-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| c7951f8e09a65e07626e7b9a272ce9911b249472 |
|
01-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Use MachineFrameInfo.getPristineRegs() to determine which callee-saved registers are available for anti-dependency breaking. Some cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 714e8bc1fc415050e557272326a75b50ac54d2bb |
|
01-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Observe hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. Do not change
operands of instructions with these properties while breaking anti-dep.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83198 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| c277ab08a24d2dbe9b4ff1a9154ea6115ed6a4e3 |
|
30-Sep-2009 |
Reid Kleckner <reid@kleckner.net> |
Fix integer overflow in instruction scheduling. This can happen if we have
basic blocks that are so long that their size overflows a short.
Also assert that overflow does not happen in the future, as requested by Evan.
This fixes PR4401.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 0dad89fa94536284d51f60868326294b725a0c61 |
|
30-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 544df3651e15f31ae2c14588c1272fd870560250 |
|
28-Sep-2009 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use KILL instead of IMPLICIT_DEF in LowerSubregs pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 8f909345bcabd0cbcb99d01d23f1d77b8b1518ec |
|
23-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix bug in kill flag updating for post-register-allocation scheduling. When the kill flag of a superreg needs to be cleared because there are one or more subregs live, we instead add implicit-defs of those subregs and leave the kill flag on the superreg. This allows us to end the live-range of the superreg without ending the live-ranges of the subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82629 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| fb2e752e4175920d0531f2afc93a23d0cdf4db14 |
|
18-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| be441c0f348a1c02a3632718832f6e2d42c4f8f0 |
|
06-Sep-2009 |
Benjamin Kramer <benny.kra@googlemail.com> |
It's a bool, so treat it like one. Fixes a MSVC warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81112 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 5e41178a6ee9a0faa2c031811d32543d7e9d0aff |
|
04-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Create our own block initializer for kill fixups as the scheduling one wasn't doing the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80958 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 1f1522839838a33e69d68656a423a244e19dffb8 |
|
01-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Add hidden flags to allow binary search of post-RA scheduling errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| a3251db21a474affaca945e3fc53f22d30d20f00 |
|
31-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Don't mark a register live at an undef use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 7886cd85b21db4498ff042a4e42aded7bf3272ee |
|
29-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Another stab at fixing up register kill flags after post-RA scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 88a589c4b39830bbeed23654521ef2f77bb87abe |
|
25-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Fixup register kills after scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80002 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 103289e9383ad1eb66caf28c9b166aebce963a35 |
|
23-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
convert LoopInfo.h and GraphWriter.h to use raw_ostream
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 2ffb0ce7dce2d5c243b90493807308af6fab0528 |
|
12-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix counting of Post-RA scheduling stalls. Improve debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| da2775767b34a503735b78422c3558815933cc94 |
|
12-Aug-2009 |
Dan Gohman <gohman@apple.com> |
This logic was accidentally inverted in r78767.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 26255adcaa5836fafe32e5e296d81df63a0fb9c5 |
|
12-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Factor out the code for finding an available register for use
in breaking an anti-dependence into a separate function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 7cd0118c367314308cf94765ac12f81020a56271 |
|
11-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Use DEBUG macro for debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| c93d8373c93159c590838957b3194900caeb8a03 |
|
11-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Add some debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 3a5f0d444cf21e2b90d5eb965bb677c7ce098546 |
|
11-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Replace DOUT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| d94a4e5d8de1145be200ff7223f98b0928462b94 |
|
10-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 845012e6d31799c7fbd1193fa1af8ee2d12e9231 |
|
01-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Use setPreservesAll and setPreservesCFG in CodeGen passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 2a3868849438a0a0ad4f9a50f2b94eb1639b554e |
|
29-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
inline the global 'getInstrOperandRegClass' function into its callers
now that TargetOperandInfo does the heavy lifting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| c23197a26f34f559ea9797de51e187087c039c42 |
|
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| c25e7581b9b8088910da31702d4ca21c4734c6d7 |
|
11-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| d923fc621ff5b5e500977edf9236c9e34e8d7ebc |
|
05-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70950 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| d9df5017040489303acb57bdd8697ef0f8bafc08 |
|
09-Apr-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix pr3954. The register scavenger asserts for inline assembly with
register destinations that are tied to source operands. The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 9e8bd0b362c034e629b9ee1f32e4e1adf037f529 |
|
11-Mar-2009 |
Duncan Sands <baldrick@free.fr> |
Add parentheses to pacify gcc-4.3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 1274ced8a3f0fd1e9a6f7c7e17d69368c4f78b90 |
|
10-Mar-2009 |
Dan Gohman <gohman@apple.com> |
Fix a post-RA scheduling liveness bug. When a basic block is being
scheduled in multiple regions, liveness data used by the
anti-dependence breaker is carried from one region to the next, however
the information reflects the state of the instructions before scheduling.
After scheduling, there may be new live range overlaps. Handle this by
pessimizing the liveness data carried between regions to the point where
it will be conservatively correct now matter how the earlier region is
scheduled. This fixes a miscompilation in 176.gcc with the post-RA
scheduler enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 47ac0f0c7c39289f5970688154e385be22b7f293 |
|
11-Feb-2009 |
Dan Gohman <gohman@apple.com> |
When scheduling a block in parts, keep track of the overall
instruction index across each part. Instruction indices are used
to make live range queries, and live ranges can extend beyond
scheduling region boundaries.
Refactor the ScheduleDAGSDNodes class some more so that it
doesn't have to worry about this additional information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| bed353d0163a6b17beecc20c23b67de9b06e7b5c |
|
11-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Consider any instruction that modifies the stack pointer to be
a scheduling region boundary. This isn't necessary for
correctness; it helps with compile time, as it avoids the need
for data- and anti-dependencies from all spills and reloads on
the stack-pointer modification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 9e64bbb322417c09f27afdf08e3946287c9df5aa |
|
11-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Factor out more code for computing register live-range informationfor
scheduling, and generalize is so that preserves state across
scheduling regions. This fixes incorrect live-range information around
terminators and labels, which are effective region boundaries.
In place of looking for terminators to anchor inter-block dependencies,
introduce special entry and exit scheduling units for this purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64254 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 770bcc7b15adbc978800db70dbb1c3c22913b52c |
|
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 6dc75fe5279e2c12bda13dcc4a1a13908de8596f |
|
06-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Move ScheduleDAGInstrs.h to be a private header. Front-ends
that used this header to select a scheduling policy should
use SchedulerRegistry.h instead (llvm-gcc and clang were
updated a while ago).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 43f07fb6c3e3d775d8e5f1eaeb380b93bb3bc09d |
|
03-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Change the post-RA scheduler to iterate through the
basic-block segments bottom-up instead of top down. This
is the first step in a general restructuring of the way
register liveness is tracked in the post-RA scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| f7119393a97c2a10757084b6bc186380f8c19a73 |
|
16-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Instead of adding dependence edges between terminator instructions
and every other instruction in their blocks to keep the terminator
instructions at the end, teach the post-RA scheduler how to operate
on ranges of instructions, and exclude terminators from the range
of instructions that get scheduled.
Also, exclude mid-block labels, such as EH_LABEL instructions, and
schedule code before them separately from code after them. This
fixes problems with the post-RA scheduler moving code past
EH_LABELs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 49bb50e0b65d4646a1d44eec3196c003c13caa96 |
|
16-Jan-2009 |
Dan Gohman <gohman@apple.com> |
If an anti-dependence uses a non-allocatable register, set AntiDepReg
to 0, to ensure that the subsequent code doesn't try to break the
dependence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 8554449e311e50f2e96db1081a17ccf7151ef7f6 |
|
16-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Fix the check for an empty basic block to check for an empty SUnits
array instead, since this is what the scheduler actually cares about.
And remove a check that is unnecessary, since it can assume that
SUnits isn't empty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62362 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 79ce4cea4701259c1aa70d59d3544ed00e9ab7f0 |
|
16-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Fix a "comparison between signed and unsigned integer expressions"
warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62327 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 2836c283bb1c14baa50994f60769d665da608ad7 |
|
16-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Initial hazard recognizer support in post-pass scheduling. This includes
a new toy hazard recognizier heuristic which attempts to direct the
scheduler to avoid clumping large groups of loads or stores too densely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 79ce276083ced01256a0eb7d80731e4948ca6e87 |
|
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.
To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
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| d68a07650cdb2e18f18f362ba533459aa10e01b6 |
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05-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Tidy up #includes, deleting a bunch of unnecessary #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| c9a5b9e38b442c2ae6b115213a07df3fcd14708d |
|
23-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Rename BuildSchedUnits to BuildSchedGraph, and refactor the
code in ScheduleDAGSDNodes' BuildSchedGraph into separate functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
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| 6c3643c41b7c00fe503a36b468ac0488d946454e |
|
19-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Use ~0u instead of -1u as the special value, to hopefully avoid
warnings on compilers that warn about such things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61263 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
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| 00dc84a2ca81be8adfee63ea0aa2a5abcb623060 |
|
16-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Eliminate the loop that walks the critical path. Instead, just track the
position in the critical path during the main instruction walk. This
eliminates the need for the CritialAntiDep DenseMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
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| 812d7506d0c55fbb0eee522cb77b62e4ab777dea |
|
16-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Enable anti-dependence breaking by default when post-RA scheduling is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
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| fde221fa0a192a00dfdbce35ceec3d2035fe1019 |
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16-Dec-2008 |
Dan Gohman <gohman@apple.com> |
When breaking an anti-dependency, don't use a register which has seen
one of its aliases defined. This is conservative, but tricky subreg
corner cases are outside the primary aim of this pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61077 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
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| 3f23744df4809eba94284e601e81489212c974d4 |
|
16-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Fix some register-alias-related bugs in the post-RA scheduler liveness
computation code. Also, avoid adding output-depenency edges when both
defs are dead, which frequently happens with EFLAGS defs.
Compute Depth and Height lazily, and always in terms of edge latency
values. For the schedulers that don't care about latency, edge latencies
are set to 1.
Eliminate Cycle and CycleBound, and LatencyPriorityQueue's Latencies array.
These are all subsumed by the Depth and Height fields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
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| 54e4c36a7349e94a84773afb56eccd4ca65b49e9 |
|
09-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Rewrite the SDep class, and simplify some of the related code.
The Cost field is removed. It was only being used in a very limited way,
to indicate when the scheduler should attempt to protect a live register,
and it isn't really needed to do that. If we ever want the scheduler to
start inserting copies in non-prohibitive situations, we'll have to
rethink some things anyway.
A Latency field is added. Instead of giving each node a single
fixed latency, each edge can have its own latency. This will eventually
be used to model various micro-architecture properties more accurately.
The PointerIntPair class and an internal union are now used, which
reduce the overall size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 2ce7f2068f13566f5a70ee779e3bb83a6cb8d942 |
|
05-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Drop the reg argument to isRegReDefinedByTwoAddr, which was redundant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60586 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 490b1833a96bf0391ebdfba7828d43a8c3512851 |
|
05-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Ignore IMPLICIT_DEF instructions when computing physreg liveness.
While they appear to provide a normal clobbering def, they don't
in the case of the awkward IMPLICIT_DEF+INSERT_SUBREG idiom. It
would be good to change INSERT_SUBREG; until then, this change
allows post-regalloc scheduling to cope in a mildly conservative
way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60583 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 80e201b8db86a88249b89527a2c7f098237925d3 |
|
04-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Use register names instead of numbers in debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60525 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| cef874ae2b97ba29f10e68d1d2eb21f28a3dc263 |
|
04-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Rewrite the liveness bookkeeping code to fix a bunch of
issues with subreg operands and tied operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| e96cc775e496260b7a42dbd6148dffb0575d1304 |
|
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Fix an inconsistency in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| e561751e98b63908c6a3a68ed5dbc0703f3369b9 |
|
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Don't charge the full latency for anti and output dependencies. This is
an area where eventually it would be good to use target-dependent
information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60498 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 0dba0e5408e999e9c46006a12a92155a961a574c |
|
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
When looking for anti-dependences on the critical path, don't bother
examining non-anti-dependence edges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| ebb0a31103f353e330ea998f1a9e283a387b6ef7 |
|
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Add a comment about callee-saved registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60495 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| a89d102b32d74fed5d3c7aeea8869a11c3074063 |
|
27-Nov-2008 |
Nick Lewycky <nicholas@mxc.ca> |
Silence a warning.
Despite changing the order of evaluation, this doesn't actually change the
meaning of the statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 878ef1d5bc3b2d12f58fbd796a4ac91b163c88f0 |
|
25-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Suppress warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60041 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 21d9003087c9a707e6cd95460136b499df358fb8 |
|
25-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Initial support for anti-dependence breaking. Currently this code does not
introduce any new spilling; it just uses unused registers.
Refactor the SUnit topological sort code out of the RRList scheduler and
make use of it to help with the post-pass scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| a1e6d363e5efa9eb1a2e7ac21a0394c870bef5ad |
|
20-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Factor out the code for verifying the work of the scheduler,
extend it a bit, and make use of it in all schedulers, to
ensure consistent checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59689 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 343f0c046702831a4a6aec951b6a297a23241a55 |
|
20-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Experimental post-pass scheduling support. Post-pass scheduling
is currently off by default, and can be enabled with
-disable-post-RA-scheduler=false.
This doesn't have a significant impact on most code yet because it doesn't
yet do anything to address anti-dependencies and it doesn't attempt to
disambiguate memory references. Also, several popular targets
don't have pipeline descriptions yet.
The majority of the changes here are splitting the SelectionDAG-specific
code out of ScheduleDAG, so that ScheduleDAG can be moved to
libLLVMCodeGen.a. The interface between ScheduleDAG-using code and
the rest of the scheduling code is somewhat rough and will evolve.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| ae73dc1448d25b02cabc7c64c86c64371453dda8 |
|
04-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Tidy up several unbeseeming casts from pointer to intptr_t.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 459525df1e003597077197b5f802bd5d9cd7d94c |
|
14-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
don't create the post-ra scheduler unless it is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45972 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| 72f159640382a16e036b63dcb9c0b427e6d5dc0a |
|
13-Jul-2007 |
Dale Johannesen <dalej@apple.com> |
Modify previous patch per review comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39817 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|
| e7e7d0d7e39d0c7c659d26b97e8081fce0fcd749 |
|
13-Jul-2007 |
Dale Johannesen <dalej@apple.com> |
Skeleton of post-RA scheduler; doesn't do anything yet.
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/PostRASchedulerList.cpp
|