Searched defs:RegIdx (Results 1 - 7 of 7) sorted by relevance

/external/llvm/lib/CodeGen/
H A DSplitKit.h277 /// intervals. Given a pair (RegIdx, ParentVNI->id), Values contains:
279 /// 1. No entry - the value is not mapped to Edit.get(RegIdx).
281 /// Edit.get(RegIdx). Each value is represented by a minimal live range at
283 /// of RegIdx in RegAssign.
295 /// getLRCalc - Return the LRCalc to use for RegIdx. In spill mode, the
298 LiveRangeCalc &getLRCalc(unsigned RegIdx) { argument
299 return LRCalc[SpillMode != SM_Partition && RegIdx != 0];
302 /// defValue - define a value in RegIdx from ParentVNI at Idx.
307 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx);
309 /// forceRecompute - Force the live range of ParentVNI in RegIdx t
[all...]
H A DLiveVariables.cpp85 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { argument
86 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
88 VirtRegInfo.grow(RegIdx);
89 return VirtRegInfo[RegIdx];
H A DSplitKit.cpp373 VNInfo *SplitEditor::defValue(unsigned RegIdx, argument
379 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
386 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id),
389 // This was the first time (RegIdx, ParentVNI) was mapped.
409 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) { argument
411 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)];
424 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
430 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, argument
437 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
440 // so always begin RegIdx
665 unsigned RegIdx = AssignI.value(); local
847 unsigned RegIdx; local
863 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx); local
951 unsigned RegIdx = RegAssign.lookup(PHIVNI->def); local
992 unsigned RegIdx = RegAssign.lookup(Idx); local
1057 unsigned RegIdx = RegAssign.lookup(ParentVNI->def); local
[all...]
/external/llvm/lib/Target/R600/InstPrinter/
H A DAMDGPUInstPrinter.cpp104 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1); local
106 O << Type << RegIdx; local
110 O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
/external/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp70 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
71 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
730 SDValue RegIdx = Node->getOperand(2); local
732 getMSACtrlReg(RegIdx), MVT::i32);
762 SDValue RegIdx = Node->getOperand(2); local
765 getMSACtrlReg(RegIdx), Value);
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp374 struct RegIdxOp RegIdx; member in union:__anon26038::MipsOperand::__anon26039
387 Op->RegIdx.Index = Index;
388 Op->RegIdx.RegInfo = RegInfo;
389 Op->RegIdx.Kind = RegKind;
399 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
400 AsmParser.WarnIfAssemblerTemporary(RegIdx.Index, StartLoc);
402 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
408 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
410 return RegIdx
[all...]
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp5242 unsigned RegIdx = 3; local
5247 RegIdx = 4;
5249 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5251 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5253 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))

Completed in 1666 milliseconds