/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 403 SDValue ShiftAmount = DAG.getConstant(NumBits, local 406 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 563 SDValue ShiftAmount = DAG.getConstant(NumBits, local 565 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
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H A D | LegalizeVectorOps.cpp | 780 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, VT); local 782 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), 783 ShiftAmount);
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 760 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); local 767 if (Opc == ISD::SRL && ShiftAmount) { 771 ShiftAmount -= 1; 774 while (ShiftAmount--)
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/external/llvm/lib/Analysis/ |
H A D | InstructionSimplify.cpp | 1976 unsigned ShiftAmount = Width - 1; local 1978 ShiftAmount = CI2->getValue().countTrailingZeros(); 1979 Lower = CI2->getValue().lshr(ShiftAmount); 1990 unsigned ShiftAmount = Width - 1; local 1992 ShiftAmount = CI2->getValue().countTrailingZeros(); 1996 Upper = CI2->getValue().ashr(ShiftAmount) + 1; 1999 Lower = CI2->getValue().ashr(ShiftAmount);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 1781 SDValue &Src, int &ShiftAmount, 1811 ShiftAmount = countTrailingZeros(NonZeroBits); 1812 MaskWidth = CountTrailingOnes_64(NonZeroBits >> ShiftAmount); 1817 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount); 1780 isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op, SDValue &Src, int &ShiftAmount, int &MaskWidth) argument
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H A D | AArch64ISelLowering.cpp | 6455 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount, argument 6467 ShiftAmount = N->getConstantOperandVal(1); 7026 int64_t ShiftAmount; local 7036 ShiftAmount = SplatValue.getSExtValue(); 7038 ShiftAmount = CVN->getSExtValue(); 7069 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) 7071 DAG.getConstant(-ShiftAmount, MVT::i32)); 7072 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBit [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 636 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) { argument 643 if (ShiftAmount > 0) { 644 m = v % ShiftAmount; 645 v = v >> ShiftAmount; 678 // ShiftAmount = number of left-shifted bits in the Hexagon instruction. 679 int ShiftAmount = VT.getSizeInBits() / 16; local 680 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) {
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/external/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.cpp | 1582 SDValue ShiftAmount = local 1589 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount); 1590 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 194 unsigned ShiftAmount; member in struct:__anon25952::AArch64Operand::ShiftedImmOp 333 return ShiftedImm.ShiftAmount; 662 unsigned Shift = ShiftedImm.ShiftAmount; 1629 unsigned ShiftAmount, 1634 Op->ShiftedImm.ShiftAmount = ShiftAmount; 2172 uint64_t ShiftAmount = 0; local 2178 ShiftAmount = 12; 2182 Operands.push_back(AArch64Operand::CreateShiftedImm(Imm, ShiftAmount, S, E, 2209 int64_t ShiftAmount local 1628 CreateShiftedImm(const MCExpr *Val, unsigned ShiftAmount, SMLoc S, SMLoc E, MCContext &Ctx) argument [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 200 unsigned &ShiftAmount); 4026 const MCExpr *ShiftAmount; local 4029 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4033 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4107 const MCExpr *ShiftAmount; local 4109 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4113 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4168 const MCExpr *ShiftAmount; local 4170 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4174 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); [all...] |