/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/ |
H A D | radeon_texture.c | 142 if (image->bo) { 143 radeon_bo_unref(image->bo); 144 image->bo = NULL; 171 image->base.Map = image->mt->bo->ptr + lvl->faces[image->base.Base.Face].offset; 188 radeon_bo_map(image->mt->bo, write_enable); 203 radeon_bo_unmap(image->mt->bo); 228 struct radeon_bo *bo = !image->mt ? image->bo : image->mt->bo; local 237 if (bo [all...] |
H A D | radeon_common_context.h | 85 struct radeon_bo *bo; member in struct:radeon_renderbuffer 169 struct radeon_bo *bo; member in struct:_radeon_texture_image 203 struct radeon_bo *bo; member in struct:radeon_tex_obj 224 struct radeon_bo *bo; member in struct:radeon_query_object 240 struct radeon_bo *bo; /** Buffer object where vertex data is stored */ member in struct:radeon_aos 251 struct radeon_bo *bo; member in struct:radeon_dma_bo 293 struct radeon_bo *bo; member in struct:radeon_swtcl_info 307 struct radeon_bo *bo; member in struct:radeon_ioctl
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/external/mesa3d/src/egl/drivers/dri2/ |
H A D | egl_dri2.h | 187 struct gbm_bo *bo; member in struct:dri2_egl_surface::__anon27096
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/external/mesa3d/src/gallium/drivers/nv50/ |
H A D | nv50_surface.c | 77 struct nouveau_bo *bo = mt->base.bo; local 102 if (!nouveau_bo_memtype(bo)) { 110 PUSH_DATAh(push, bo->offset + offset); 111 PUSH_DATA (push, bo->offset + offset); 122 PUSH_DATAh(push, bo->offset + offset); 123 PUSH_DATA (push, bo->offset + offset); 279 struct nouveau_bo *bo = mt->base.bo; local 293 PUSH_DATAh(push, bo 337 struct nouveau_bo *bo = mt->base.bo; local [all...] |
/external/mesa3d/src/gallium/drivers/nvc0/ |
H A D | nvc0_surface.c | 80 struct nouveau_bo *bo = mt->base.bo; local 109 if (nouveau_bo_memtype(bo)) { 117 PUSH_DATAh(push, bo->offset + offset); 118 PUSH_DATA (push, bo->offset + offset); 129 PUSH_DATAh(push, bo->offset + offset); 130 PUSH_DATA (push, bo->offset + offset); 302 if (likely(nouveau_bo_memtype(res->bo))) {
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/external/mesa3d/src/gallium/drivers/r600/ |
H A D | evergreen_compute_internal.c | 116 res->bo = NULL; 213 struct r600_resource *bo, 216 assert(bo); 219 u32 rr = r600_context_bo_reloc(ctx, bo, usage); 225 struct r600_resource *bo) 227 switch (bo->b.b.format) 259 struct r600_resource* bo, 286 (struct pipe_resource *)bo, &rat_templ); 339 struct r600_resource* bo, 352 res->bo 211 evergreen_emit_ctx_reloc( struct r600_context *ctx, struct r600_resource *bo, enum radeon_bo_usage usage) argument 223 evergreen_compute_get_gpu_format( struct number_type_and_format* fmt, struct r600_resource *bo) argument 256 evergreen_set_rat( struct r600_pipe_compute *pipe, int id, struct r600_resource* bo, int start, int size) argument 337 evergreen_set_export( struct r600_pipe_compute *pipe, struct r600_resource* bo, int offset, int size) argument 377 evergreen_set_tmp_ring( struct r600_pipe_compute *pipe, struct r600_resource* bo, int offset, int size, int se) argument [all...] |
H A D | r600.h | 109 struct r600_resource *bo; member in struct:r600_pipe_reg 124 struct r600_resource *bo; member in struct:r600_block_reloc 215 struct r600_resource *bo, 225 struct r600_resource *bo, 228 #define r600_pipe_state_add_reg_bo(state, offset, value, bo, usage) _r600_pipe_state_add_reg_bo(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
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H A D | r600_state_common.c | 466 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL); 828 r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->ps_shader->current->bo); 856 r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->vs_shader->current->bo); 1377 struct r600_resource *bo, 1384 if (bo) assert(usage); 1392 state->regs[state->nregs].bo = bo; 1410 struct r600_resource *bo, 1413 if (bo) assert(usage); 1418 state->regs[state->nregs].bo 1373 _r600_pipe_state_add_reg_bo(struct r600_context *ctx, struct r600_pipe_state *state, uint32_t offset, uint32_t value, uint32_t range_id, uint32_t block_id, struct r600_resource *bo, enum radeon_bo_usage usage) argument 1408 r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state, uint32_t offset, uint32_t value, struct r600_resource *bo, enum radeon_bo_usage usage) argument [all...] |
/external/mesa3d/src/gallium/drivers/radeonsi/ |
H A D | radeonsi_pipe.h | 54 struct si_resource *bo; member in struct:r600_pipe_fences 98 unsigned index; /* in the shared bo */
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/external/mesa3d/src/gallium/state_trackers/xorg/ |
H A D | xorg_driver.c | 1186 struct kms_bo *bo; local 1203 if (kms_bo_create(ms->kms, attr, &bo)) 1206 if (kms_bo_get_prop(bo, KMS_PITCH, &stride)) 1209 if (kms_bo_get_prop(bo, KMS_HANDLE, &handle)) 1227 FatalError("%s: could not takedown old bo", __func__); 1232 ms->root_bo = bo; 1238 kms_bo_destroy(&bo);
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/external/mesa3d/src/mesa/drivers/dri/r200/ |
H A D | radeon_fbo.c | 67 if (rrb && rrb->bo) { 68 radeon_bo_unref(rrb->bo); 171 ret = radeon_bo_map(rrb->bo, !!(mode & GL_MAP_WRITE_BIT)); 174 tiled_s8z24_map = rrb->bo->ptr; 185 radeon_bo_unmap(rrb->bo); 209 ret = radeon_bo_map(rrb->bo, !!(mode & GL_MAP_WRITE_BIT)); 213 tiled_z16_map = rrb->bo->ptr; 224 radeon_bo_unmap(rrb->bo); 246 if (!rrb || !rrb->bo) { 281 ok = rmesa->vtbl.blit(ctx, rrb->bo, rr 971 radeon_renderbuffer_set_bo(struct radeon_renderbuffer *rb, struct radeon_bo *bo) argument [all...] |
H A D | radeon_texture.c | 142 if (image->bo) { 143 radeon_bo_unref(image->bo); 144 image->bo = NULL; 171 image->base.Map = image->mt->bo->ptr + lvl->faces[image->base.Base.Face].offset; 188 radeon_bo_map(image->mt->bo, write_enable); 203 radeon_bo_unmap(image->mt->bo); 228 struct radeon_bo *bo = !image->mt ? image->bo : image->mt->bo; local 237 if (bo [all...] |
/external/mesa3d/src/mesa/drivers/dri/radeon/ |
H A D | radeon_fbo.c | 67 if (rrb && rrb->bo) { 68 radeon_bo_unref(rrb->bo); 171 ret = radeon_bo_map(rrb->bo, !!(mode & GL_MAP_WRITE_BIT)); 174 tiled_s8z24_map = rrb->bo->ptr; 185 radeon_bo_unmap(rrb->bo); 209 ret = radeon_bo_map(rrb->bo, !!(mode & GL_MAP_WRITE_BIT)); 213 tiled_z16_map = rrb->bo->ptr; 224 radeon_bo_unmap(rrb->bo); 246 if (!rrb || !rrb->bo) { 281 ok = rmesa->vtbl.blit(ctx, rrb->bo, rr 971 radeon_renderbuffer_set_bo(struct radeon_renderbuffer *rb, struct radeon_bo *bo) argument [all...] |
H A D | radeon_texture.c | 142 if (image->bo) { 143 radeon_bo_unref(image->bo); 144 image->bo = NULL; 171 image->base.Map = image->mt->bo->ptr + lvl->faces[image->base.Base.Face].offset; 188 radeon_bo_map(image->mt->bo, write_enable); 203 radeon_bo_unmap(image->mt->bo); 228 struct radeon_bo *bo = !image->mt ? image->bo : image->mt->bo; local 237 if (bo [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/rtasm/ |
H A D | rtasm_ppc.c | 408 unsigned bo:5; member in struct:xl_inst::__anon13734 418 emit_xl(struct ppc_function *p, uint op, uint bo, uint bi, uint bh, argument 423 inst.inst.bo = bo; 440 debug_printf(" bo: %d 0x%x\n", i.inst.bo, i.inst.bo);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r600/ |
H A D | r600_state_common.c | 466 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL); 828 r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->ps_shader->current->bo); 856 r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->vs_shader->current->bo); 1377 struct r600_resource *bo, 1384 if (bo) assert(usage); 1392 state->regs[state->nregs].bo = bo; 1410 struct r600_resource *bo, 1413 if (bo) assert(usage); 1418 state->regs[state->nregs].bo 1373 _r600_pipe_state_add_reg_bo(struct r600_context *ctx, struct r600_pipe_state *state, uint32_t offset, uint32_t value, uint32_t range_id, uint32_t block_id, struct r600_resource *bo, enum radeon_bo_usage usage) argument 1408 r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state, uint32_t offset, uint32_t value, struct r600_resource *bo, enum radeon_bo_usage usage) argument [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/winsys/radeon/drm/ |
H A D | radeon_drm_bo.c | 97 static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo) argument 99 assert(bo->vtbl == &radeon_bo_vtbl); 100 return (struct radeon_bo *)bo; 134 struct radeon_bo *bo = NULL; local 137 bo = radeon_bo(_buf); 144 bo = radeon_bo(base_buf); 147 return bo; 152 struct radeon_bo *bo = get_radeon_bo(_buf); local 154 while (p_atomic_read(&bo->num_active_ioctls)) { 159 /*if (bo 177 struct radeon_bo *bo = get_radeon_bo(_buf); local 366 struct radeon_bo *bo = radeon_bo(_buf); local 398 struct radeon_bo *bo = (struct radeon_bo*)buf; local 542 struct radeon_bo *bo; local 622 struct radeon_bo *bo = radeon_bo(_buf); local 718 struct radeon_bo *bo = get_radeon_bo(_buf); local 757 struct radeon_bo *bo = get_radeon_bo(_buf); local 850 struct radeon_bo *bo; local 947 struct radeon_bo *bo = get_radeon_bo(buffer); local [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
H A D | brw_wm_surface_state.c | 724 drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL; local 743 if (bo) { 744 surf[1] = bo->offset; /* reloc */ 747 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 749 bo, 0, I915_GEM_DOMAIN_SAMPLER, 0); 800 surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */ 816 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 818 intelObj->mt->region->bo, 829 drm_intel_bo *bo, 848 surf[1] = bo 828 brw_create_constant_surface(struct brw_context *brw, drm_intel_bo *bo, uint32_t offset, int width, uint32_t *out_offset) argument 883 drm_intel_bo *bo = local 1042 drm_intel_bo *bo = NULL; local 1369 drm_intel_bo *bo = intel_bufferobj_buffer(intel, intel_bo, INTEL_READ); local [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | Scalarizer.cpp | 95 BinarySplitter(BinaryOperator &bo) : BO(bo) {} argument
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/external/mesa3d/src/gallium/auxiliary/rtasm/ |
H A D | rtasm_ppc.c | 408 unsigned bo:5; member in struct:xl_inst::__anon27145 418 emit_xl(struct ppc_function *p, uint op, uint bo, uint bi, uint bh, argument 423 inst.inst.bo = bo; 440 debug_printf(" bo: %d 0x%x\n", i.inst.bo, i.inst.bo);
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/external/mesa3d/src/gallium/winsys/radeon/drm/ |
H A D | radeon_drm_bo.c | 97 static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo) argument 99 assert(bo->vtbl == &radeon_bo_vtbl); 100 return (struct radeon_bo *)bo; 134 struct radeon_bo *bo = NULL; local 137 bo = radeon_bo(_buf); 144 bo = radeon_bo(base_buf); 147 return bo; 152 struct radeon_bo *bo = get_radeon_bo(_buf); local 154 while (p_atomic_read(&bo->num_active_ioctls)) { 159 /*if (bo 177 struct radeon_bo *bo = get_radeon_bo(_buf); local 366 struct radeon_bo *bo = radeon_bo(_buf); local 398 struct radeon_bo *bo = (struct radeon_bo*)buf; local 542 struct radeon_bo *bo; local 622 struct radeon_bo *bo = radeon_bo(_buf); local 718 struct radeon_bo *bo = get_radeon_bo(_buf); local 757 struct radeon_bo *bo = get_radeon_bo(_buf); local 850 struct radeon_bo *bo; local 947 struct radeon_bo *bo = get_radeon_bo(buffer); local [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_wm_surface_state.c | 724 drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL; local 743 if (bo) { 744 surf[1] = bo->offset; /* reloc */ 747 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 749 bo, 0, I915_GEM_DOMAIN_SAMPLER, 0); 800 surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */ 816 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 818 intelObj->mt->region->bo, 829 drm_intel_bo *bo, 848 surf[1] = bo 828 brw_create_constant_surface(struct brw_context *brw, drm_intel_bo *bo, uint32_t offset, int width, uint32_t *out_offset) argument 883 drm_intel_bo *bo = local 1042 drm_intel_bo *bo = NULL; local 1369 drm_intel_bo *bo = intel_bufferobj_buffer(intel, intel_bo, INTEL_READ); local [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/intel/ |
H A D | intel_context.h | 114 drm_intel_bo *bo; member in struct:intel_sync_object 121 drm_intel_bo *bo; member in struct:intel_batchbuffer 202 drm_intel_bo *bo, 255 drm_intel_bo *bo; member in struct:intel_context::__anon14474
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/ |
H A D | radeon_common_context.h | 85 struct radeon_bo *bo; member in struct:radeon_renderbuffer 169 struct radeon_bo *bo; member in struct:_radeon_texture_image 203 struct radeon_bo *bo; member in struct:radeon_tex_obj 224 struct radeon_bo *bo; member in struct:radeon_query_object 240 struct radeon_bo *bo; /** Buffer object where vertex data is stored */ member in struct:radeon_aos 251 struct radeon_bo *bo; member in struct:radeon_dma_bo 293 struct radeon_bo *bo; member in struct:radeon_swtcl_info 307 struct radeon_bo *bo; member in struct:radeon_ioctl
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/external/mesa3d/src/mesa/drivers/dri/intel/ |
H A D | intel_context.h | 114 drm_intel_bo *bo; member in struct:intel_sync_object 121 drm_intel_bo *bo; member in struct:intel_batchbuffer 202 drm_intel_bo *bo, 255 drm_intel_bo *bo; member in struct:intel_context::__anon27885
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