/external/llvm/lib/Target/AArch64/ |
H A D | AArch64LoadStoreOptimizer.cpp | 339 static void trackRegDefsUses(MachineInstr *MI, BitVector &ModifiedRegs, argument 342 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 343 MachineOperand &MO = MI->getOperand(i); 417 MachineInstr *MI = MBBI; local 420 if (MI->isDebugValue()) 426 if (Opc == MI->getOpcode() && MI->getOperand(2).isImm()) { 437 unsigned MIBaseReg = MI->getOperand(1).getReg(); 438 int MIOffset = MI->getOperand(2).getImm(); 445 if (MI 606 isMatchingUpdateInsn(MachineInstr *MI, unsigned BaseReg, int Offset) argument 669 MachineInstr *MI = MBBI; local 722 MachineInstr *MI = MBBI; local 766 MachineInstr *MI = MBBI; local 834 MachineInstr *MI = MBBI; local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.h | 30 MachineBasicBlock::iterator MI, 41 MachineBasicBlock::iterator MI,
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.h | 38 MachineBasicBlock::iterator MI, 42 MachineBasicBlock::iterator MI,
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16FrameLowering.h | 34 MachineBasicBlock::iterator MI, 39 MachineBasicBlock::iterator MI,
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/external/llvm/lib/Target/R600/ |
H A D | R600ControlFlowFinalizer.cpp | 224 bool IsTrivialInst(MachineInstr *MI) const { 225 switch (MI->getOpcode()) { 280 bool isCompatibleWithClause(const MachineInstr *MI, argument 283 for (MachineInstr::const_mop_iterator I = MI->operands_begin(), 284 E = MI->operands_end(); I != E; ++I) { 342 void getLiteral(MachineInstr *MI, std::vector<int64_t> &Lits) const { argument 350 TII->getSrcs(MI); 459 void CounterPropagateAddr(MachineInstr *MI, unsigned Addr) const { argument 460 MI->getOperand(0).setImm(Addr + MI 466 MachineInstr *MI = *It; local 510 MachineBasicBlock::iterator MI = I; variable [all...] |
H A D | AMDGPUMCInstLower.h | 42 void lower(const MachineInstr *MI, MCInst &OutMI) const;
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H A D | R600OptimizeVectorRegisters.cpp | 66 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { argument 67 assert(MI->getOpcode() == AMDGPU::REG_SEQUENCE); 98 MachineInstr *RebuildVector(RegSeqInfo *MI, 131 bool R600VectorRegMerger::canSwizzle(const MachineInstr &MI) 133 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) 135 switch (MI.getOpcode()) { 233 void R600VectorRegMerger::RemoveMI(MachineInstr *MI) { argument 237 MIs.erase(std::find(MIs.begin(), MIs.end(), MI), MIs.end()); 242 MIs.erase(std::find(MIs.begin(), MIs.end(), MI), MI 246 SwizzleInput(MachineInstr &MI, const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const argument 328 MachineInstr *MI = MII; local [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreFrameLowering.h | 35 MachineBasicBlock::iterator MI, 39 MachineBasicBlock::iterator MI,
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H A D | XCoreInstrInfo.cpp | 64 XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{ argument 65 int Opcode = MI->getOpcode(); 68 if ((MI->getOperand(1).isFI()) && // is a stack slot 69 (MI->getOperand(2).isImm()) && // the imm is zero 70 (isZeroImm(MI->getOperand(2)))) 72 FrameIndex = MI->getOperand(1).getIndex(); 73 return MI->getOperand(0).getReg(); 85 XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI, argument 87 int Opcode = MI->getOpcode(); 90 if ((MI 440 loadImmediate( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const argument [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUConvertToISA.cpp | 57 MachineInstr &MI = *I; local 58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
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H A D | R600ISelLowering.h | 27 virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, 41 void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
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H A D | AMDGPURegisterInfo.cpp | 38 void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, argument
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPURegisterInfo.cpp | 38 void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, argument
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/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | AsmPrinterHandler.h | 50 virtual void beginInstruction(const MachineInstr *MI) = 0;
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXReplaceImageHandles.cpp | 37 bool processInstr(MachineInstr &MI); 55 MachineInstr &MI = *I; local 56 Changed |= processInstr(MI); 72 bool NVPTXReplaceImageHandles::processInstr(MachineInstr &MI) { argument 73 MachineFunction &MF = *MI.getParent()->getParent(); 75 switch (MI.getOpcode()) { 119 MachineOperand &TexHandle = MI.getOperand(4); 120 MachineOperand &SampHandle = MI.getOperand(5); 143 MachineOperand &SurfHandle = MI.getOperand(1); 165 MachineOperand &SurfHandle = MI 319 MachineInstr *MI = MRI.getVRegDef(Op.getReg()); local [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZMCInstLower.cpp | 92 void SystemZMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { argument 93 OutMI.setOpcode(MI->getOpcode()); 94 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { 95 const MachineOperand &MO = MI->getOperand(I);
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/external/llvm/include/llvm/ADT/ |
H A D | EquivalenceClasses.h | 45 /// for (EquivalenceClasses<int>::member_iterator MI = EC.member_begin(I); 46 /// MI != EC.member_end(); ++MI) // Loop over members in this set. 47 /// cerr << *MI << " "; // Print member. 126 member_iterator MI = RHS.member_begin(I); local 127 member_iterator LeaderIt = member_begin(insert(*MI)); 128 for (++MI; MI != member_end(); ++MI) 129 unionSets(LeaderIt, member_begin(insert(*MI))); 166 member_iterator MI = findLeader(V); local 175 member_iterator MI = findLeader(insert(V)); local [all...] |
H A D | UniqueVector.h | 60 typename std::map<T, unsigned>::const_iterator MI = Map.find(Entry); local 63 if (MI != Map.end()) return MI->second;
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/external/llvm/lib/CodeGen/ |
H A D | CriticalAntiDepBreaker.h | 90 void Observe(MachineInstr *MI, unsigned Count, 97 void PrescanInstruction(MachineInstr *MI); 98 void ScanInstruction(MachineInstr *MI, unsigned Count);
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H A D | ExpandISelPseudos.cpp | 56 MachineInstr *MI = MBBI++; local 58 // If MI is a pseudo, expand it. 59 if (MI->usesCustomInsertionHook()) { 62 TLI->EmitInstrWithCustomInserter(MI, MBB);
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H A D | AggressiveAntiDepBreaker.cpp | 190 void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count, argument 195 GetPassthruRegs(MI, PassthruRegs); 196 PrescanInstruction(MI, Count, PassthruRegs); 197 ScanInstruction(MI, Count); 200 DEBUG(MI->dump()); 224 bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI, 236 Op = MI->findRegisterUseOperand(Reg, true); 238 Op = MI->findRegisterDefOperand(Reg); 243 void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI, 245 for (unsigned i = 0, e = MI [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FrameLowering.h | 51 MachineBasicBlock::iterator MI, 56 MachineBasicBlock::iterator MI, 69 MachineBasicBlock::iterator MI) const override;
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCAsmPrinter.cpp | 80 void EmitInstruction(const MachineInstr *MI) override; 82 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O); 84 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, 87 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, 143 void PPCAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, argument 146 const MachineOperand &MO = MI->getOperand(OpNo); 218 bool PPCAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, argument 228 return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O); 233 if (!MI->getOperand(OpNo).isReg() || 234 OpNo+1 == MI 256 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument 306 EmitInstruction(const MachineInstr *MI) argument [all...] |
/external/llvm/lib/Target/Sparc/Disassembler/ |
H A D | SparcDisassembler.cpp | 209 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, 267 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, 270 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address, argument 285 status = DecodeRD(MI, rd, Address, Decoder); 291 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 297 MI.addOperand(MCOperand::CreateImm(simm13)); 299 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 305 status = DecodeRD(MI, rd, Address, Decoder); 362 uint64_t Width, MCInst &MI, 365 return Dis->tryAddingSymbolicOperand(MI, Valu 360 tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const void *Decoder) argument 369 DecodeCall(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) argument 379 DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) argument 386 DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) argument 420 DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) argument 448 DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) argument [all...] |
/external/clang/lib/StaticAnalyzer/Checkers/ |
H A D | CheckObjCInstMethSignature.cpp | 107 MapTy::iterator MI = IMeths.find(S); local 109 if (MI == IMeths.end() || MI->second == nullptr) 113 ObjCMethodDecl *MethDerived = MI->second; 114 MI->second = nullptr;
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