/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | AsmPrinter.cpp | 670 unsigned Reg; local 672 Reg = MI->getOperand(0).getReg(); 677 MI->getOperand(0).getIndex(), Reg); 680 if (Reg == 0) { 689 OS << AP.TM.getRegisterInfo()->getName(Reg);
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/external/valgrind/main/VEX/priv/ |
H A D | host_mips_isel.c | 1890 vassert(hregClass(ri->Mrh.Reg.reg) == HRcGPR(env->mode64)); 1891 vassert(hregIsVirtual(ri->Mrh.Reg.reg)); 1960 vassert(hregClass(ri->Mrh.Reg.reg) == HRcInt32); 1961 vassert(hregIsVirtual(ri->Mrh.Reg.reg)); 1999 vassert(hregClass(ri->Mrh.Reg.reg) == HRcGPR(env->mode64)); 2000 vassert(hregIsVirtual(ri->Mrh.Reg.reg)); 2517 addInstr(env, MIPSInstr_Alu(Malu_AND, a2, sa->Mrh.Reg.reg, 2581 addInstr(env, MIPSInstr_Alu(Malu_AND, a2, sa->Mrh.Reg.reg, 2649 addInstr(env, MIPSInstr_Alu(Malu_AND, a2, sa->Mrh.Reg.reg, 2717 addInstr(env, MIPSInstr_Alu(Malu_AND, a2, sa->Mrh.Reg [all...] |
H A D | host_mips_defs.h | 197 Mam_IR, /* Immediate (signed 16-bit) + Reg */ 240 } Reg; member in union:__anon31925::__anon31926
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H A D | host_mips_defs.c | 1023 op->Mrh.Reg.reg = reg; 1038 ppHRegMIPS(op->Mrh.Reg.reg, mode64); 1055 addHRegUse(u, HRmRead, op->Mrh.Reg.reg); 1069 op->Mrh.Reg.reg = lookupHRegRemap(m, op->Mrh.Reg.reg); 2304 if (hregNumber(i->Min.Alu.srcR->Mrh.Reg.reg) 2864 UInt r_srcR = immR ? (-1) /*bogus */ : iregNo(srcR->Mrh.Reg.reg, 2977 UInt r_srcR = immR ? (-1) /*bogus */ : iregNo(srcR->Mrh.Reg.reg,
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H A D | host_ppc_isel.c | 1275 r_src = ri->Pri.Reg; 2536 vassert(hregClass(ri->Prh.Reg.reg) == HRcGPR(env->mode64)); 2537 vassert(hregIsVirtual(ri->Prh.Reg.reg)); 2596 vassert(hregClass(ri->Pri.Reg) == HRcGPR(env->mode64)); 2597 vassert(hregIsVirtual(ri->Pri.Reg)); 2649 vassert(hregClass(ri->Prh.Reg.reg) == HRcGPR(env->mode64)); 2650 vassert(hregIsVirtual(ri->Prh.Reg.reg)); 2694 vassert(hregClass(ri->Prh.Reg.reg) == HRcGPR(env->mode64)); 2695 vassert(hregIsVirtual(ri->Prh.Reg.reg));
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H A D | host_x86_isel.c | 1632 vassert(hregClass(rmi->Xrmi.Reg.reg) == HRcInt32); 1633 vassert(hregIsVirtual(rmi->Xrmi.Reg.reg)); 1695 vassert(hregClass(ri->Xri.Reg.reg) == HRcInt32); 1696 vassert(hregIsVirtual(ri->Xri.Reg.reg)); 1740 vassert(hregClass(rm->Xrm.Reg.reg) == HRcInt32); 1741 vassert(hregIsVirtual(rm->Xrm.Reg.reg));
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H A D | host_amd64_isel.c | 2035 vassert(hregClass(rmi->Armi.Reg.reg) == HRcInt64); 2036 vassert(hregIsVirtual(rmi->Armi.Reg.reg)); 2107 vassert(hregClass(ri->Ari.Reg.reg) == HRcInt64); 2108 vassert(hregIsVirtual(ri->Ari.Reg.reg)); 2161 vassert(hregClass(rm->Arm.Reg.reg) == HRcInt64); 2162 vassert(hregIsVirtual(rm->Arm.Reg.reg));
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/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGNodes.h | 1652 unsigned Reg; member in class:RegisterSDNode 1655 : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) { 1659 unsigned getReg() const { return Reg; }
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/external/llvm/lib/Target/ARM/ |
H A D | ARMConstantIslandPass.cpp | 1814 unsigned Reg = CmpMI->getOperand(0).getReg(); local 1818 isARMLowRegister(Reg)) { 1823 .addReg(Reg).addMBB(DestBB,Br.MI->getOperand(0).getTargetFlags());
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H A D | ARMISelLowering.cpp | 2700 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); local 2701 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2714 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); 2715 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 3032 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); local 3033 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 3905 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); local 3906 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 3932 unsigned Reg = StringSwitch<unsigned>(RegName) local 3935 if (Reg) 6785 unsigned Reg = SavedRegs[i]; local 7203 unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass); local [all...] |
H A D | ARMISelDAGToDAG.cpp | 135 bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) { argument 138 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 172 /// register can be improved, but it is wrong to substitute Reg+Reg for 173 /// Reg in an asm, because the load or store opcode would have to change. 212 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local 213 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) { 1442 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8; local 1445 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
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H A D | PPCISelLowering.cpp | 2289 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); local 2290 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, 8857 unsigned Reg = StringSwitch<unsigned>(RegName) local 8864 if (Reg) 8865 return Reg;
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/external/llvm/lib/Target/X86/Disassembler/ |
H A D | X86Disassembler.cpp | 173 /// @param reg - The Reg to append. 174 static void translateRegister(MCInst &mcInst, Reg reg) {
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | PathDiagnostic.cpp | 1151 if (Optional<loc::MemRegionVal> Reg = SV.getAs<loc::MemRegionVal>()) { 1152 SVal PSV = State->getSVal(Reg->getRegion());
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 329 unsigned Reg = State.AllocateReg(RegList, NbRegs); local 330 State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 1030 unsigned Reg = MO.getReg(); local 1031 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
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/external/llvm/lib/Target/X86/ |
H A D | X86CodeEmitter.cpp | 183 unsigned Reg = MO.getReg(); local 184 if (X86II::isX86_64NonExtLowByteReg(Reg))
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H A D | X86ISelLowering.cpp | 1962 unsigned Reg = FuncInfo->getSRetReturnReg(); local 1963 assert(Reg && 1965 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 2302 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); local 2303 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2345 unsigned Reg = FuncInfo->getSRetReturnReg(); local 2346 if (!Reg) { 2348 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy)); 2349 FuncInfo->setSRetReturnReg(Reg); 2351 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVal 3329 unsigned Reg = VA.getLocReg(); local [all...] |
/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 2092 unsigned Reg, EVT VT) const { 2096 if (!MRI.isLiveIn(Reg)) { 2098 MRI.addLiveIn(Reg, VirtualRegister); 2100 VirtualRegister = MRI.getLiveInVirtReg(Reg); 2090 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1728 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); local 1729 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3665 unsigned Reg = StringSwitch<unsigned>(RegName) local 3668 if (Reg) 3669 return Reg; 3691 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass); local 3692 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT); 3923 const std::string Reg = local 3925 int RegNo = atoi(Reg.c_str());
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