Searched refs:TM (Results 151 - 175 of 414) sorted by relevance

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/external/llvm/lib/ExecutionEngine/JIT/
H A DJIT.cpp78 TargetMachine *TM) {
85 if (TargetJITInfo *TJ = TM->getJITInfo()) {
86 return new JIT(M, *TM, *TJ, JMM, GVsWithCode);
139 : ExecutionEngine(M), TM(tm), TJI(tji),
142 setDataLayout(TM.getDataLayout());
147 JCE = createEmitter(*this, JMM, TM);
155 M->setDataLayout(TM.getDataLayout());
160 if (TM.addPassesToEmitMachineCode(PM, *JCE, !getVerifyModules())) {
174 delete &TM;
188 M->setDataLayout(TM
74 createJIT(Module *M, std::string *ErrorStr, JITMemoryManager *JMM, bool GVsWithCode, TargetMachine *TM) argument
[all...]
H A DJIT.h58 TargetMachine &TM; // The current target we are compiling to member in class:llvm::JIT
189 TargetMachine *TM);
197 TargetMachine *getTargetMachine() override { return &TM; }
/external/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp72 RegDefsUses(TargetMachine &TM);
170 : MachineFunctionPass(ID), TM(tm) { }
242 TargetMachine &TM; member in class:__anon26049::Filler
288 RegDefsUses::RegDefsUses(TargetMachine &TM) argument
289 : TRI(*TM.getRegisterInfo()), Defs(TRI.getNumRegs(), false),
505 if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
519 static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
551 if (TM.getSubtarget<MipsSubtarget>().isTargetNaCl()) {
559 || I->modifiesRegister(Mips::SP, TM.getRegisterInfo()))
574 RegDefsUses RegDU(TM);
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H A DMipsInstrInfo.cpp35 TM(tm), UncondBrOpc(UncondBr) {}
37 const MipsInstrInfo *MipsInstrInfo::create(MipsTargetMachine &TM) { argument
38 if (TM.getSubtargetImpl()->inMips16Mode())
39 return llvm::createMips16InstrInfo(TM);
41 return llvm::createMipsSEInstrInfo(TM);
H A DMipsSEISelDAGToDAG.h24 explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM) : MipsDAGToDAGISel(TM) {} argument
113 FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM);
/external/llvm/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp57 HexagonExpandPredSpillCode(const HexagonTargetMachine& TM) : argument
58 MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {
199 llvm::createHexagonExpandPredSpillCode(const HexagonTargetMachine &TM) { argument
200 return new HexagonExpandPredSpillCode(TM);
H A DHexagonSplitTFRCondSets.cpp66 HexagonSplitTFRCondSets(const HexagonTargetMachine& TM) : argument
67 MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {
235 llvm::createHexagonSplitTFRCondSets(const HexagonTargetMachine &TM) { argument
236 return new HexagonSplitTFRCondSets(TM);
H A DHexagonCallingConvLower.h49 const TargetMachine &TM; member in class:llvm::Hexagon_CCState
56 Hexagon_CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &TM,
64 const TargetMachine &getTarget() const { return TM; }
H A DHexagonMachineScheduler.h57 VLIWResourceModel(const TargetMachine &TM, const TargetSchedModel *SM) : argument
59 ResourcesModel = TM.getInstrInfo()->CreateTargetScheduleState(&TM, nullptr);
/external/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp36 SparcTargetMachine &TM; member in class:__anon26140::SparcDAGToDAGISel
41 TM(tm) {
69 unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
219 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) { argument
220 return new SparcDAGToDAGISel(TM);
/external/llvm/lib/CodeGen/
H A DDFAPacketizer.cpp130 bool IsPostRA) : TM(MF.getTarget()), MF(MF) {
131 TII = TM.getInstrInfo();
132 ResourceTracker = TII->CreateTargetScheduleState(&TM, nullptr);
/external/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp92 const TargetMachine *TM; member in class:__anon26188::FixupLEAPass
154 TM = &Func.getTarget();
155 const X86Subtarget &ST = TM->getSubtarget<X86Subtarget>();
159 TII = static_cast<const X86InstrInfo *>(TM->getInstrInfo());
221 InstrDistance += TII->getInstrLatency(TM->getInstrItineraryData(), CurInst);
336 if (TM->getSubtarget<X86Subtarget>().isSLM())
H A DX86TargetMachine.cpp103 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM) argument
104 : TargetPassConfig(TM, PM) {}
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUAsmPrinter.cpp41 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
59 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
H A DR600ExpandSpecialInstrs.cpp47 FunctionPass *llvm::createR600ExpandSpecialInstrsPass(TargetMachine &TM) { argument
48 return new R600ExpandSpecialInstrsPass(TM);
H A DR600InstrInfo.h35 AMDGPUTargetMachine &TM; member in class:llvm::R600InstrInfo
63 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
/external/llvm/lib/CodeGen/AsmPrinter/
H A DAsmPrinterInlineAsm.cpp88 const MCAsmInfo *MCAI = TM.getMCAsmInfo();
93 emitInlineAsmEnd(TM.getSubtarget<MCSubtargetInfo>(), nullptr);
130 std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
131 TM.getTargetTriple(), TM.getTargetCPU(), TM.getTargetFeatureString()));
143 TM.getTarget().createMCAsmParser(*STI, *Parser, *MII, MCOptions));
503 const DataLayout *DL = TM.getDataLayout();
H A DDwarfCFIException.cpp70 TLOF.emitPersonalityValue(Asm->OutStreamer, Asm->TM, Sym);
112 TLOF.getCFIPersonalitySymbol(Per, *Asm->Mang, Asm->TM, MMI);
/external/llvm/lib/Target/MSP430/
H A DMSP430AsmPrinter.cpp42 MSP430AsmPrinter(TargetMachine &TM, MCStreamer &Streamer) argument
43 : AsmPrinter(TM, Streamer) {}
H A DMSP430MCInstLower.cpp53 const DataLayout *DL = Printer.TM.getDataLayout();
70 const DataLayout *DL = Printer.TM.getDataLayout();
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUAsmPrinter.cpp41 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
59 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
H A DR600ExpandSpecialInstrs.cpp47 FunctionPass *llvm::createR600ExpandSpecialInstrsPass(TargetMachine &TM) { argument
48 return new R600ExpandSpecialInstrsPass(TM);
H A DR600InstrInfo.h35 AMDGPUTargetMachine &TM; member in class:llvm::R600InstrInfo
63 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
/external/llvm/lib/Target/PowerPC/
H A DPPCCTRLoops.cpp87 PPCCTRLoops() : FunctionPass(ID), TM(nullptr) {
90 PPCCTRLoops(PPCTargetMachine &TM) : FunctionPass(ID), TM(&TM) { argument
109 PPCTargetMachine *TM; member in struct:__anon26082::PPCCTRLoops
154 FunctionPass *llvm::createPPCCTRLoops(PPCTargetMachine &TM) { argument
155 return new PPCCTRLoops(TM);
215 if (!TM)
217 const TargetLowering *TLI = TM->getTargetLowering();
385 if (!TM)
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/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/
H A Dlp_bld_debug.cpp278 TargetMachine *TM = T->createTargetMachine(Triple, sys::getHostCPUName(), "", options); local
280 TargetMachine *TM = T->createTargetMachine(Triple, sys::getHostCPUName(), ""); local
282 TargetMachine *TM = T->createTargetMachine(Triple, ""); local
285 const TargetInstrInfo *TII = TM->getInstrInfo();

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