Searched refs:ra (Results 101 - 125 of 199) sorted by relevance

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/external/openssl/crypto/aes/asm/
H A Daes-mips.pl32 ($gp,$tp,$sp,$fp,$ra)=map("\$$_",(3,28..31));
48 # ($gp,$sp,$fp,$ra)=map("\$$_",(28..31));
114 .frame $sp,0,$ra
353 jr $ra
360 .frame $sp,$FRAMESIZE,$ra
369 $REG_S $ra,$FRAMESIZE-1*$SZREG($sp)
416 $REG_L $ra,$FRAMESIZE-1*$SZREG($sp)
435 jr $ra
445 .frame $sp,0,$ra
690 jr $ra
[all...]
/external/chromium_org/v8/src/arm64/
H A Dassembler-arm64.h1397 const Register& ra);
1406 const Register& ra);
1418 const Register& ra);
1424 const Register& ra);
1430 const Register& ra);
1436 const Register& ra);
1777 static Instr Ra(CPURegister ra) {
1778 DCHECK(ra.code() != kSPRegInternalCode);
1779 return ra.code() << Ra_offset;
2041 const Register& ra,
[all...]
H A Dassembler-arm64.cc1422 const Register& ra,
1424 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd));
1440 const Register& ra) {
1441 DCHECK(AreSameSizeAndType(rd, rn, rm, ra));
1442 DataProcessing3Source(rd, rn, rm, ra, MADD);
1458 const Register& ra) {
1459 DCHECK(AreSameSizeAndType(rd, rn, rm, ra));
1460 DataProcessing3Source(rd, rn, rm, ra, MSUB);
1467 const Register& ra) {
1468 DCHECK(rd.Is64Bits() && ra
1419 DataProcessing3Source(const Register& rd, const Register& rn, const Register& rm, const Register& ra, DataProcessing3SourceOp op) argument
1437 madd(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1455 msub(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1464 smaddl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1474 smsubl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1484 umaddl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
1494 umsubl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument
[all...]
/external/vixl/src/a64/
H A Dassembler-a64.h1057 const Register& ra);
1063 const Register& ra);
1069 const Register& ra);
1075 const Register& ra);
1081 const Register& ra);
1087 const Register& ra);
1417 static Instr Ra(CPURegister ra) {
1418 VIXL_ASSERT(ra.code() != kSPRegInternalCode);
1419 return ra.code() << Ra_offset;
1809 const Register& ra,
[all...]
/external/chromium_org/v8/src/mips/
H A Dregexp-macro-assembler-mips.cc91 * area is overwritten with the ra register by the RegExp code. When doing a
599 __ MultiPush(argument_registers | registers_to_retain | ra.bit());
788 // Restore registers s0..s7 and return (restoring ra to pc).
789 __ MultiPop(registers_to_retain | ra.bit());
1250 __ pop(ra);
1251 __ Addu(t5, ra, Operand(masm_->CodeObject()));
1258 __ Subu(ra, ra, Operand(masm_->CodeObject()));
1259 __ push(ra);
H A Dbuiltins-mips.cc92 // -- ra : return address
122 // -- ra : return address
153 // -- ra : return address
191 // -- ra : return address
327 // -- ra : return address
339 // -- ra : return address
813 __ Jump(ra);
876 (a0.bit() | a1.bit() | ra.bit() | fp.bit()) & ~sp.bit();
915 (a0.bit() | a1.bit() | ra.bit() | fp.bit()) & ~sp.bit();
926 __ Push(ra, f
[all...]
H A Dcode-stubs-mips.h247 masm->MultiPush((kJSCallerSaved | ra.bit()) & ~scratch1_.bit());
258 masm->MultiPop((kJSCallerSaved | ra.bit()) & ~scratch1_.bit());
H A Dlithium-codegen-mips.h394 codegen_->masm_->push(ra);
401 codegen_->masm_->push(ra);
/external/chromium_org/v8/src/mips64/
H A Dregexp-macro-assembler-mips64.cc83 * - fp[72] ra Return from RegExp code (ra). kReturnAddress
127 * area is overwritten with the ra register by the RegExp code. When doing a
643 __ MultiPush(argument_registers | registers_to_retain | ra.bit());
834 // Restore registers s0..s7 and return (restoring ra to pc).
835 __ MultiPop(registers_to_retain | ra.bit());
1296 __ pop(ra);
1297 __ Daddu(t1, ra, Operand(masm_->CodeObject()));
1304 __ Dsubu(ra, ra, Operan
[all...]
H A Dcodegen-mips64.cc289 __ jr(ra);
488 __ jr(ra);
591 // Register ra contains the return address.
618 __ push(ra);
690 __ ld(ra, MemOperand(sp, 0));
727 __ pop(ra);
739 // Register ra contains the return address.
760 value.bit() | key.bit() | receiver.bit() | target_map.bit() | ra.bit());
805 value.bit() | key.bit() | receiver.bit() | target_map.bit() | ra.bit());
861 __ pop(ra);
[all...]
H A Dbuiltins-mips64.cc91 // -- ra : return address
121 // -- ra : return address
152 // -- ra : return address
190 // -- ra : return address
326 // -- ra : return address
338 // -- ra : return address
828 __ Jump(ra);
890 (a0.bit() | a1.bit() | ra.bit() | fp.bit()) & ~sp.bit();
929 (a0.bit() | a1.bit() | ra.bit() | fp.bit()) & ~sp.bit();
940 __ Push(ra, f
[all...]
H A Dcode-stubs-mips64.h249 masm->MultiPush((kJSCallerSaved | ra.bit()) & ~scratch1_.bit());
260 masm->MultiPop((kJSCallerSaved | ra.bit()) & ~scratch1_.bit());
H A Dlithium-codegen-mips64.h395 codegen_->masm_->push(ra);
402 codegen_->masm_->push(ra);
/external/dhcpcd/
H A Dconfigure.c172 int dhcp, ra; local
174 dhcp = ra = 0;
176 ra = 1;
224 if ((dhcp && iface->state->new) || (ra && iface->ras)) {
275 if (ra) {
/external/chromium_org/third_party/skia/samplecode/
H A DSampleRegion.cpp133 static void test_union_bug_1505668(SkRegion* ra, SkRegion* rb, SkRegion* rc) { argument
144 make_rgn(ra, 0, 1, 315, 1496, SK_ARRAY_COUNT(dataA), dataA);
159 rc->op(*ra, *rb, SkRegion::kUnion_Op);
/external/skia/samplecode/
H A DSampleRegion.cpp133 static void test_union_bug_1505668(SkRegion* ra, SkRegion* rb, SkRegion* rc) { argument
144 make_rgn(ra, 0, 1, 315, 1496, SK_ARRAY_COUNT(dataA), dataA);
159 rc->op(*ra, *rb, SkRegion::kUnion_Op);
/external/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips4.s18 dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
21 daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
84 tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips5.s18 dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
21 daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
82 tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips5-wrong-error.s36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/libsepol/src/
H A Dservices.c827 struct role_allow *ra; local
920 for (ra = policydb->role_allow; ra; ra = ra->next) {
921 if (scontext->role == ra->role &&
922 tcontext->role == ra->new_role)
925 if (!ra)
/external/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips5-wrong-error.s36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/llvm/test/MC/Mips/mips3/
H A Dinvalid-mips5-wrong-error.s36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/llvm/test/MC/Mips/mips4/
H A Dinvalid-mips5-wrong-error.s36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips3.s28 tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips5-wrong-error.s38 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction

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