Searched defs:bo (Results 176 - 200 of 213) sorted by last modified time

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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
H A Dgen7_wm_surface_state.c127 assert ((mcs_mt->region->bo->offset & 0xfff) == 0);
130 surf->ss6.mcs_enabled.mcs_base_address = mcs_mt->region->bo->offset >> 12;
131 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
134 mcs_mt->region->bo,
242 drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL; local
260 if (bo) {
261 surf->ss1.base_addr = bo->offset; /* reloc */
267 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
270 bo, 0,
352 intelObj->mt->region->bo
404 gen7_create_constant_surface(struct brw_context *brw, drm_intel_bo *bo, uint32_t offset, int width, uint32_t *out_offset) argument
[all...]
H A Dintel_buffer_objects.c206 drm_intel_bo_references(intel->batch.bo, intel_obj->buffer);
210 /* Replace the current busy bo with fresh data. */
256 if (drm_intel_bo_references(intel->batch.bo, intel_obj->buffer)) {
328 if (drm_intel_bo_references(intel->batch.bo, intel_obj->buffer)) {
491 if (!intel->upload.bo)
495 drm_intel_bo_subdata(intel->upload.bo,
502 drm_intel_bo_unreference(intel->upload.bo);
503 intel->upload.bo = NULL;
513 intel->upload.bo = drm_intel_bo_alloc(intel->bufmgr, "upload", size, 0);
525 if (intel->upload.bo
729 drm_intel_bo *bo = intel_bufferobj_buffer(intel, intel_obj, INTEL_READ); local
[all...]
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/intel/
H A Dintel_buffer_objects.c206 drm_intel_bo_references(intel->batch.bo, intel_obj->buffer);
210 /* Replace the current busy bo with fresh data. */
256 if (drm_intel_bo_references(intel->batch.bo, intel_obj->buffer)) {
328 if (drm_intel_bo_references(intel->batch.bo, intel_obj->buffer)) {
491 if (!intel->upload.bo)
495 drm_intel_bo_subdata(intel->upload.bo,
502 drm_intel_bo_unreference(intel->upload.bo);
503 intel->upload.bo = NULL;
513 intel->upload.bo = drm_intel_bo_alloc(intel->bufmgr, "upload", size, 0);
525 if (intel->upload.bo
729 drm_intel_bo *bo = intel_bufferobj_buffer(intel, intel_obj, INTEL_READ); local
[all...]
H A Dintel_context.h114 drm_intel_bo *bo; member in struct:intel_sync_object
121 drm_intel_bo *bo; member in struct:intel_batchbuffer
202 drm_intel_bo *bo,
255 drm_intel_bo *bo; member in struct:intel_context::__anon14474
H A Dintel_mipmap_tree.h77 drm_intel_bo *bo; member in struct:intel_miptree_map
264 /* Offset into region bo where miptree starts:
H A Dintel_regions.h61 drm_intel_bo *bo; /**< buffer manager's buffer */ member in struct:intel_region
72 uint32_t name; /**< Global name for the bo */
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/nouveau/
H A Dnouveau_array.h39 struct nouveau_bo *bo; member in struct:nouveau_array
H A Dnouveau_bufferobj.h32 struct nouveau_bo *bo; member in struct:nouveau_bufferobj
38 (_mesa_is_bufferobj(x) ? to_nouveau_bufferobj(x)->bo : NULL)
H A Dnouveau_fbo.h35 struct nouveau_bo *bo; member in struct:nouveau_framebuffer::__anon14478
H A Dnouveau_local.h77 PUSH_RELOC(struct nouveau_pushbuf *push, struct nouveau_bo *bo, uint32_t offset, argument
80 nouveau_pushbuf_reloc(push, bo, offset, flags, vor, tor);
103 struct nouveau_bo *bo, uint32_t offset, uint32_t access)
106 bo, offset, access | NOUVEAU_BO_LOW, 0, 0); local
107 PUSH_DATA(push, bo->offset + offset);
112 struct nouveau_bo *bo, uint32_t data, uint32_t access,
116 bo, data, access | NOUVEAU_BO_OR, vor, tor); local
118 if (bo->flags & NOUVEAU_BO_VRAM)
126 struct nouveau_bo *bo, uint32_t data, uint32_t access,
130 bo, dat local
102 PUSH_MTHDl(struct nouveau_pushbuf *push, int subc, int mthd, int bin, struct nouveau_bo *bo, uint32_t offset, uint32_t access) argument
111 PUSH_MTHDs(struct nouveau_pushbuf *push, int subc, int mthd, int bin, struct nouveau_bo *bo, uint32_t data, uint32_t access, uint32_t vor, uint32_t tor) argument
125 PUSH_MTHD(struct nouveau_pushbuf *push, int subc, int mthd, int bin, struct nouveau_bo *bo, uint32_t data, uint32_t access, uint32_t vor, uint32_t tor) argument
[all...]
H A Dnouveau_scratch.c31 * Returns a pointer to a chunk of 'size' bytes long GART memory. 'bo'
36 struct nouveau_bo **bo, unsigned *offset)
44 nouveau_bo_ref(scratch->bo[scratch->index], bo);
52 nouveau_bo_ref(scratch->bo[scratch->index], bo);
54 nouveau_bo_map(*bo, NOUVEAU_BO_WR, client);
55 buf = scratch->buf = (*bo)->map;
62 NOUVEAU_BO_MAP, 0, size, NULL, bo); local
64 nouveau_bo_map(*bo, NOUVEAU_BO_W
35 nouveau_get_scratch(struct gl_context *ctx, unsigned size, struct nouveau_bo **bo, unsigned *offset) argument
[all...]
H A Dnouveau_scratch.h34 struct nouveau_bo *bo[NOUVEAU_SCRATCH_COUNT]; member in struct:nouveau_scratch_state
43 struct nouveau_bo **bo, unsigned *offset);
H A Dnouveau_surface.h37 struct nouveau_bo *bo; member in struct:nouveau_surface
H A Dnouveau_vbo_t.c91 nouveau_bo_ref(NULL, &a->bo);
268 struct nouveau_bo *bo, int *pdelta)
273 if (a->bo == bo) {
293 struct nouveau_bo *bo[NUM_VERTEX_ATTRS]; local
307 bo[i] = NULL;
311 nouveau_bo_ref(to_nouveau_bufferobj(obj)->bo, &bo[i]);
319 &bo[i], &offset[i]);
329 dirty |= check_update_array(a, offset[i], bo[
267 check_update_array(struct nouveau_array *a, unsigned offset, struct nouveau_bo *bo, int *pdelta) argument
[all...]
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
H A Dr200_blit.c102 struct radeon_bo *bo,
152 if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
154 if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
292 OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
298 struct radeon_bo *bo,
335 if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
337 if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
351 OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
353 OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
516 "offset [%d x %d], format %s, bo
99 emit_tx_setup(struct r200_context *r200, gl_format src_mesa_format, gl_format dst_mesa_format, struct radeon_bo *bo, intptr_t offset, unsigned width, unsigned height, unsigned pitch) argument
297 emit_cb_setup(struct r200_context *r200, struct radeon_bo *bo, intptr_t offset, gl_format mesa_format, unsigned pitch, unsigned width, unsigned height) argument
[all...]
H A Dr200_cmdbuf.c222 struct radeon_bo *bo,
235 OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
280 rmesa->radeon.tcl.aos[i+0].bo,
286 rmesa->radeon.tcl.aos[i+1].bo,
294 rmesa->radeon.tcl.aos[nr-1].bo,
220 r200EmitVertexAOS( r200ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset ) argument
H A Dradeon_buffer_objects.h41 struct radeon_bo *bo; member in struct:radeon_buffer_object
H A Dradeon_common_context.c352 struct radeon_bo *depth_bo = NULL, *bo; local
469 if (rb->bo) {
470 uint32_t name = radeon_gem_name_bo(rb->bo);
490 bo = depth_bo;
491 radeon_bo_ref(bo);
496 bo = radeon_bo_open(radeon->radeonScreen->bom,
503 if (bo == NULL) {
509 ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch);
514 radeon_bo_unref(bo);
515 bo
[all...]
H A Dradeon_common_context.h85 struct radeon_bo *bo; member in struct:radeon_renderbuffer
169 struct radeon_bo *bo; member in struct:_radeon_texture_image
203 struct radeon_bo *bo; member in struct:radeon_tex_obj
224 struct radeon_bo *bo; member in struct:radeon_query_object
240 struct radeon_bo *bo; /** Buffer object where vertex data is stored */ member in struct:radeon_aos
251 struct radeon_bo *bo; member in struct:radeon_dma_bo
293 struct radeon_bo *bo; member in struct:radeon_swtcl_info
307 struct radeon_bo *bo; member in struct:radeon_ioctl
H A Dradeon_dma.c144 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32);
148 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32);
155 radeon_bo_map(aos->bo, 1);
156 out = (uint32_t*)((char*)aos->bo->ptr + aos->offset);
166 radeon_bo_unmap(aos->bo);
182 radeonAllocDmaRegion( rmesa, &aos->bo, &aos->offset, size * 4, 32 );
186 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32);
194 radeon_bo_map(aos->bo, 1);
195 out = (float*)((char*)aos->bo->ptr + aos->offset);
201 radeon_bo_unmap(aos->bo);
332 radeon_bo_is_idle(struct radeon_bo* bo) argument
[all...]
H A Dradeon_fbo.c67 if (rrb && rrb->bo) {
68 radeon_bo_unref(rrb->bo);
171 ret = radeon_bo_map(rrb->bo, !!(mode & GL_MAP_WRITE_BIT));
174 tiled_s8z24_map = rrb->bo->ptr;
185 radeon_bo_unmap(rrb->bo);
209 ret = radeon_bo_map(rrb->bo, !!(mode & GL_MAP_WRITE_BIT));
213 tiled_z16_map = rrb->bo->ptr;
224 radeon_bo_unmap(rrb->bo);
246 if (!rrb || !rrb->bo) {
281 ok = rmesa->vtbl.blit(ctx, rrb->bo, rr
971 radeon_renderbuffer_set_bo(struct radeon_renderbuffer *rb, struct radeon_bo *bo) argument
[all...]
H A Dradeon_mipmap_tree.h63 struct radeon_bo *bo; member in struct:_radeon_mipmap_tree
H A Dradeon_screen.h110 struct radeon_bo *bo; member in struct:__DRIimageRec
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
H A Dradeon_blit.c96 struct radeon_bo *bo,
143 if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
145 if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
170 OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
176 struct radeon_bo *bo,
211 if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
214 if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
226 OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
228 OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
394 "offset [%d x %d], format %s, bo
94 emit_tx_setup(struct r100_context *r100, gl_format mesa_format, struct radeon_bo *bo, intptr_t offset, unsigned width, unsigned height, unsigned pitch) argument
175 emit_cb_setup(struct r100_context *r100, struct radeon_bo *bo, intptr_t offset, gl_format mesa_format, unsigned pitch, unsigned width, unsigned height) argument
[all...]
H A Dradeon_buffer_objects.h41 struct radeon_bo *bo; member in struct:radeon_buffer_object

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