Searched refs:miss (Results 51 - 75 of 109) sorted by relevance

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/external/oprofile/events/mips/1004K/
H A Devents31 event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
60 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
62 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline
95 event:0x3d counters:0 um:zero minimum:500 name:SELF_INTERVENTION_LATENCY : 61-0 Latency from miss detection to self intervention
96 event:0x3e counters:0 um:zero minimum:500 name:READ_RESPONSE_LATENCY : 62-0 Read latency from miss detection until critical dword of response is returned
111 event:0x40d counters:1 um:zero minimum:500 name:LOAD_MISS_INSNS : 13-1 Cacheable load instructions that miss in the cache
134 event:0x424 counters:1 um:zero minimum:500 name:INTERVENTION_MISS_STALLS : 36-1 Cache coherence intervention processing stall cycles due to an earlier miss
139 event:0x425 counters:1 um:zero minimum:500 name:DCACHE_MISS_STALLS : 37-1 Stall cycles due to a data cache miss
141 event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
172 event:0x43d counters:1 um:zero minimum:500 name:SELF_INTERVENTION_COUNT : 61-1 Self intervention requests on miss detectio
[all...]
/external/oprofile/events/mips/34K/
H A Devents31 event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
59 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
61 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline
88 event:0x3e counters:0 um:zero minimum:500 name:READ_RESPONSE_LATENCY : 62-0 Read latency from miss detection until critical dword of response is returned
103 event:0x40d counters:1 um:zero minimum:500 name:LOAD_MISS_INSNS : 13-1 Cacheable load instructions that miss in the cache
130 event:0x425 counters:1 um:zero minimum:500 name:DCACHE_MISS_STALLS : 37-1 Stall cycles due to a data cache miss
132 event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
158 event:0x43e counters:1 um:zero minimum:500 name:READ_RESPONSE_COUNT : 62-1 Read requests on miss detection
/external/chromium_org/v8/src/ic/arm/
H A Dic-arm.cc40 // elements: Property dictionary. It is not clobbered if a jump to the miss
42 // name: Property name. It is not clobbered if a jump to the miss label is
44 // result: Register for the result. It is only updated if a jump to the miss
46 // one of these in the case of not jumping to the miss label.
51 static void GenerateDictionaryLoad(MacroAssembler* masm, Label* miss, argument
62 NameDictionaryLookupStub::GeneratePositiveLookup(masm, miss, &done, elements,
74 __ b(ne, miss);
84 // elements: Property dictionary. It is not clobbered if a jump to the miss
86 // name: Property name. It is not clobbered if a jump to the miss label is
93 static void GenerateDictionaryStore(MacroAssembler* masm, Label* miss, argument
592 Label miss; local
900 Label miss; local
[all...]
/external/chromium_org/v8/src/ic/arm64/
H A Dic-arm64.cc35 // elements: Property dictionary. It is not clobbered if a jump to the miss
37 // name: Property name. It is not clobbered if a jump to the miss label is
39 // result: Register for the result. It is only updated if a jump to the miss
44 static void GenerateDictionaryLoad(MacroAssembler* masm, Label* miss, argument
54 NameDictionaryLookupStub::GeneratePositiveLookup(masm, miss, &done, elements,
66 __ B(ne, miss);
76 // elements: Property dictionary. It is not clobbered if a jump to the miss
78 // name: Property name. It is not clobbered if a jump to the miss label is
84 static void GenerateDictionaryStore(MacroAssembler* masm, Label* miss, argument
93 NameDictionaryLookupStub::GeneratePositiveLookup(masm, miss,
632 Label miss; local
930 Label miss; local
[all...]
/external/chromium_org/v8/src/ic/mips/
H A Dic-mips.cc38 // elements: Property dictionary. It is not clobbered if a jump to the miss
40 // name: Property name. It is not clobbered if a jump to the miss label is
42 // result: Register for the result. It is only updated if a jump to the miss
44 // one of these in the case of not jumping to the miss label.
51 static void GenerateDictionaryLoad(MacroAssembler* masm, Label* miss, argument
62 NameDictionaryLookupStub::GeneratePositiveLookup(masm, miss, &done, elements,
75 __ Branch(miss, ne, at, Operand(zero_reg));
85 // elements: Property dictionary. It is not clobbered if a jump to the miss
87 // name: Property name. It is not clobbered if a jump to the miss label is
96 static void GenerateDictionaryStore(MacroAssembler* masm, Label* miss, argument
599 Label miss; local
904 Label miss; local
[all...]
/external/chromium_org/v8/src/ic/mips64/
H A Dic-mips64.cc38 // elements: Property dictionary. It is not clobbered if a jump to the miss
40 // name: Property name. It is not clobbered if a jump to the miss label is
42 // result: Register for the result. It is only updated if a jump to the miss
44 // one of these in the case of not jumping to the miss label.
51 static void GenerateDictionaryLoad(MacroAssembler* masm, Label* miss, argument
62 NameDictionaryLookupStub::GeneratePositiveLookup(masm, miss, &done, elements,
75 __ Branch(miss, ne, at, Operand(zero_reg));
85 // elements: Property dictionary. It is not clobbered if a jump to the miss
87 // name: Property name. It is not clobbered if a jump to the miss label is
96 static void GenerateDictionaryStore(MacroAssembler* masm, Label* miss, argument
604 Label miss; local
913 Label miss; local
[all...]
/external/oprofile/events/x86-64/family11h/
H A Dunit_masks76 0x02 DCT0 Page miss
79 0x10 DCT1 Page miss
105 0x01 Probe miss
128 0x20 DEV miss
163 0x04 Read Block (Dcache load miss refill)
165 0x10 Read Block Modified (Dcache store miss refill)
187 0x04 The number of cycles spent in non-speculative phase (including cache miss penalty)
H A Devents68 event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_HIT : L1 ITLB miss and L2 ITLB hit
69 event:0x85 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_MISS : L1 ITLB miss and L2 ITLB miss
/external/oprofile/events/mips/25K/
H A Devents52 event:0x1a counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : I-Cache miss
57 event:0x1b counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : D-Cache miss
64 event:0x1e counters:0,1 um:zero minimum:500 name:L2_MISSES : L2 Cache miss
/external/oprofile/events/mips/24K/
H A Devents31 event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
55 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
57 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline
95 event:0x40d counters:1 um:zero minimum:500 name:LOAD_MISS_INSNS : 13-1 Cacheable load instructions that miss in the cache
119 event:0x425 counters:1 um:zero minimum:500 name:DCACHE_MISS_STALLS : 37-1 Stall cycles due to a data cache miss
121 event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
/external/oprofile/events/x86-64/hammer/
H A Dunit_masks70 0x02 Page miss
90 0x01 Probe miss
118 0x04 GART miss
157 0x04 Read Block (Dcache load miss refill)
159 0x10 Read Block Modified (Dcache store miss refill)
180 0x04 The number of cycles spent in non-speculative phase (including cache miss penalty)
H A Devents68 event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_HIT : L1 ITLB miss and L2 ITLB hit
69 event:0x85 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_MISS : L1 ITLB miss and L2 ITLB miss
/external/chromium_org/v8/src/mips/
H A Dcode-stubs-mips.cc110 ExternalReference miss) {
128 __ CallExternalReference(miss, param_count);
625 Label miss; local
626 CompareICStub_CheckInputType(masm, lhs, a2, left(), &miss);
627 CompareICStub_CheckInputType(masm, rhs, a3, right(), &miss);
790 __ bind(&miss);
1447 Label miss; local
1449 __ Branch(&miss, ne, function, Operand(at));
1451 __ Branch(&miss, ne, map, Operand(at));
1455 __ bind(&miss);
109 GenerateLightweightMiss(MacroAssembler* masm, ExternalReference miss) argument
1588 Label miss; local
2475 Label initialize, done, miss, megamorphic, not_array_function; local
2757 Label miss; local
2833 Label miss; local
2884 ExternalReference miss = ExternalReference(IC_Utility(id), local
3472 Label miss; local
3498 Label miss; local
3588 Label miss; local
3629 Label miss; local
3672 Label miss; local
3758 Label miss; local
3777 Label miss; local
3796 ExternalReference miss = local
3849 GenerateNegativeLookup(MacroAssembler* masm, Label* miss, Label* done, Register receiver, Register properties, Handle<Name> name, Register scratch0) argument
3931 GeneratePositiveLookup(MacroAssembler* masm, Label* miss, Label* done, Register elements, Register name, Register scratch1, Register scratch2) argument
[all...]
/external/chromium_org/v8/src/mips64/
H A Dcode-stubs-mips64.cc109 ExternalReference miss) {
127 __ CallExternalReference(miss, param_count);
619 Label miss; local
620 CompareICStub_CheckInputType(masm, lhs, a2, left(), &miss);
621 CompareICStub_CheckInputType(masm, rhs, a3, right(), &miss);
785 __ bind(&miss);
1446 Label miss; local
1448 __ Branch(&miss, ne, function, Operand(at));
1450 __ Branch(&miss, ne, map, Operand(at));
1454 __ bind(&miss);
108 GenerateLightweightMiss(MacroAssembler* masm, ExternalReference miss) argument
1587 Label miss; local
2507 Label initialize, done, miss, megamorphic, not_array_function; local
2829 Label miss; local
2905 Label miss; local
2956 ExternalReference miss = ExternalReference(IC_Utility(id), local
3509 Label miss; local
3535 Label miss; local
3625 Label miss; local
3666 Label miss; local
3709 Label miss; local
3795 Label miss; local
3814 Label miss; local
3833 ExternalReference miss = local
3886 GenerateNegativeLookup(MacroAssembler* masm, Label* miss, Label* done, Register receiver, Register properties, Handle<Name> name, Register scratch0) argument
3969 GeneratePositiveLookup(MacroAssembler* masm, Label* miss, Label* done, Register elements, Register name, Register scratch1, Register scratch2) argument
[all...]
/external/oprofile/events/mips/rm7000/
H A Devents25 event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache miss stall cycles (cycles where both cache miss tokens taken and a third try is requested)
/external/chromium_org/net/disk_cache/blockfile/
H A Dstats.cc47 "Open miss",
49 "Create miss",
310 int Stats::GetRatio(Counters hit, Counters miss) const {
315 ratio /= (GetCounter(hit) + GetCounter(miss));
/external/oprofile/events/x86-64/family10/
H A Dunit_masks80 0x02 DCT0 Page miss
83 0x10 DCT1 Page miss
111 0x01 Probe miss
137 0x04 GART miss
140 0x20 DEV miss
176 0x04 Read Block (Dcache load miss refill)
178 0x10 Read Block Modified (Dcache store miss refill)
240 0x04 Cycles in non-speculative phase (including cache miss penalty)
241 0x08 Cache miss penalty in cycles
/external/chromium_org/third_party/libxml/src/
H A Dgentest.py945 for miss in missing_list:
946 lst.write("%s: %d :" % (miss[1], miss[0]))
948 for n in missing_types[miss[1]]:
/external/oprofile/events/mips/sb1/
H A Devents42 event:0x3 counters:1,2,3 um:zero minimum:500 name:DCACHE_READ_MISS :Dcache read results in a miss
46 event:0xc counters:1,2,3 um:zero minimum:500 name:DCACHE_READ_MISS :Dcache read results in a miss
/external/chromium_org/v8/src/arm/
H A Dcode-stubs-arm.h313 Label* miss,
321 Label* miss,
/external/chromium_org/v8/src/arm64/
H A Dcode-stubs-arm64.h348 Label* miss,
356 Label* miss,
/external/chromium_org/v8/src/ic/x64/
H A Dic-x64.cc408 Label miss; local
417 &miss, // When not a string.
418 &miss, // When not a number.
419 &miss, // When index out of range.
427 __ bind(&miss);
771 // Dictionary load failed, go slow (but don't miss).
855 // Cache miss: Jump to runtime.
892 Label miss; local
895 GenerateDictionaryStore(masm, &miss, dictionary, name, value, r8, r9);
900 __ bind(&miss);
[all...]
/external/oprofile/events/i386/westmere/
H A Devents17 event:0x0c counters:0,1,2,3 um:x01 minimum:200000 name:MEM_STORE_RETIRED : Retired stores that miss the DTLB (Precise Event)
33 event:0x2e counters:0,1,2,3 um:longest_lat_cache minimum:100000 name:LONGEST_LAT_CACHE : Longest latency cache miss
46 event:0x85 counters:0,1,2,3 um:itlb_misses minimum:200000 name:ITLB_MISSES : ITLB miss
70 event:0xcb counters:0,1,2,3 um:mem_load_retired minimum:200000 name:MEM_LOAD_RETIRED : Retired loads that miss the DTLB (Precise Event)
/external/linux-tools-perf/perf-3.12.0/tools/perf/util/
H A Dsort.c601 u64 hit, miss; local
609 miss = m & PERF_MEM_TLB_MISS;
628 if (miss)
629 strncat(out, " miss", sz - l);
678 u64 hit, miss; local
686 miss = m & PERF_MEM_LVL_MISS;
705 if (miss)
706 strncat(out, " miss", sz - l);
/external/oprofile/events/i386/atom/
H A Dunit_masks44 0x02 misses Icache miss
98 0x02 l2_miss Retired loads that miss the L2 cache (precise event)
99 0x04 dtlb_miss Retired loads that miss the DTLB (precise event)

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