Searched refs:MCInst (Results 76 - 100 of 180) sorted by relevance

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/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp17 #include "llvm/MC/MCInst.h"
101 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
120 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
127 DecodeStatus AddThumbPredicate(MCInst&) const;
128 void UpdateThumbVFPPredicate(MCInst&) const;
150 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
152 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
155 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
158 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
160 static DecodeStatus DecodetcGPRRegisterClass(MCInst
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/external/llvm/include/llvm/MC/
H A DMCObjectSymbolizer.h26 class MCInst;
50 bool tryAddingSymbolicOperand(MCInst &MI, raw_ostream &cStream,
H A DMCELFStreamer.h25 class MCInst;
90 void EmitInstToFragment(const MCInst &Inst, const MCSubtargetInfo &) override;
91 void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &) override;
H A DMCExternalSymbolizer.h48 bool tryAddingSymbolicOperand(MCInst &MI, raw_ostream &CommentStream,
H A DMCInstPrinter.h1 //===-- MCInstPrinter.h - Convert an MCInst to target assembly syntax -----===//
17 class MCInst;
32 /// that converts an MCInst to valid target assembly syntax.
69 /// printInst - Print the specified MCInst to the specified raw_ostream.
71 virtual void printInst(const MCInst *MI, raw_ostream &OS,
H A DMCWinCOFFStreamer.h21 class MCInst;
66 void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &STI) override;
H A DMCObjectStreamer.h41 virtual void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo&) = 0;
98 void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo& STI) override;
102 virtual void EmitInstToFragment(const MCInst &Inst, const MCSubtargetInfo &);
/external/llvm/lib/Target/PowerPC/
H A DPPC.h32 class MCInst;
46 void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp23 #include "llvm/MC/MCInst.h"
53 static void LowerLargeShift(MCInst& Inst) {
86 static void LowerDextDins(MCInst& InstIn) {
145 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
154 MCInst TmpInst = MI;
204 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
226 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
249 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
271 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
293 getJumpOffset16OpValue(const MCInst
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H A DMipsNaClELFStreamer.cpp50 bool isIndirectJump(const MCInst &MI) {
60 bool isStackPointerFirstOperand(const MCInst &MI) {
65 bool isCall(const MCInst &MI, bool *IsIndirectCall) {
95 MCInst MaskInst;
105 void sandboxIndirectJump(const MCInst &MI, const MCSubtargetInfo &STI) {
116 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx,
138 void EmitInstruction(const MCInst &Inst,
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
H A DR600MCCodeEmitter.cpp24 #include "llvm/MC/MCInst.h"
53 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
57 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
61 void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
63 void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
64 void EmitDst(const MCInst &MI, raw_ostream &OS) const;
65 void EmitALU(const MCInst &MI, unsigned numSrc,
68 void EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
70 void EmitFCInstr(const MCInst &MI, raw_ostream &OS) const;
87 bool isFlagSet(const MCInst
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/external/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp13 #include "llvm/MC/MCInst.h"
32 virtual DecodeStatus getInstruction(MCInst &instr,
172 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
179 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
185 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
191 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
197 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
203 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
209 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
215 static DecodeStatus DecodeVSFRCRegisterClass(MCInst
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DR600MCCodeEmitter.cpp24 #include "llvm/MC/MCInst.h"
53 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
57 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
61 void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
63 void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
64 void EmitDst(const MCInst &MI, raw_ostream &OS) const;
65 void EmitALU(const MCInst &MI, unsigned numSrc,
68 void EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
70 void EmitFCInstr(const MCInst &MI, raw_ostream &OS) const;
87 bool isFlagSet(const MCInst
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/external/llvm/lib/Target/NVPTX/InstPrinter/
H A DNVPTXInstPrinter.cpp10 // Print MCInst instructions to .ptx format.
18 #include "llvm/MC/MCInst.h"
74 void NVPTXInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
82 void NVPTXInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
96 void NVPTXInstPrinter::printCvtMode(const MCInst *MI, int OpNum, raw_ostream &O,
146 void NVPTXInstPrinter::printCmpMode(const MCInst *MI, int OpNum, raw_ostream &O,
219 void NVPTXInstPrinter::printLdStCode(const MCInst *MI, int OpNum,
267 void NVPTXInstPrinter::printMemOperand(const MCInst *MI, int OpNum,
283 void NVPTXInstPrinter::printProtoIdent(const MCInst *MI, int OpNum,
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCAsmBackend.cpp15 #include "llvm/MC/MCInst.h"
52 bool mayNeedRelaxation(const MCInst &Inst) const override {
60 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
10 // This class prints an AArch64 MCInst to a .s file.
19 #include "llvm/MC/MCInst.h"
55 void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
616 void AArch64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
668 bool AArch64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
891 void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
905 void AArch64InstPrinter::printHexImm(const MCInst *MI, unsigned OpNo,
911 void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
924 void AArch64InstPrinter::printVRegOperand(const MCInst *M
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/external/lldb/source/Plugins/Disassembler/llvm/
H A DDisassemblerLLVMC.h21 class MCInst;
48 uint64_t GetMCInst (const uint8_t *opcode_data, size_t opcode_data_len, lldb::addr_t pc, llvm::MCInst &mc_inst);
49 uint64_t PrintMCInst (llvm::MCInst &mc_inst, char *output_buffer, size_t out_buffer_len);
51 bool CanBranch (llvm::MCInst &mc_inst);
/external/llvm/lib/MC/
H A DMCDisassembler.cpp19 bool MCDisassembler::tryAddingSymbolicOperand(MCInst &Inst, int64_t Value,
/external/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.h29 void getNoopForMachoTarget(MCInst &NopInst) const override;
/external/llvm/lib/Target/R600/MCTargetDesc/
H A DSIMCCodeEmitter.cpp21 #include "llvm/MC/MCInst.h"
57 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
62 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
129 void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
172 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
/external/llvm/lib/Target/Sparc/
H A DSparc.h27 class MCInst;
36 MCInst &OutMI,
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
18 #include "llvm/MC/MCInst.h"
75 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
117 bool needsExpansion(MCInst &Inst);
121 bool expandInstruction(MCInst &Inst, SMLoc IDLoc,
122 SmallVectorImpl<MCInst> &Instructions);
124 bool expandLoadImm(MCInst &Inst, SMLoc IDLoc,
125 SmallVectorImpl<MCInst> &Instructions);
127 bool expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
128 SmallVectorImpl<MCInst>
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/external/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp22 #include "llvm/MC/MCInst.h"
75 static bool translateInstruction(MCInst &target,
131 X86GenericDisassembler::getInstruction(MCInst &instr,
170 /// register, and appends it as an operand to an MCInst.
172 /// @param mcInst - The MCInst to append to.
174 static void translateRegister(MCInst &mcInst, Reg reg) {
187 /// immediate Value in the MCInst.
200 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
204 /// if it adds an operand to the MCInst and false otherwise.
207 uint64_t Width, MCInst
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/external/llvm/include/llvm/MC/MCAnalysis/
H A DMCAtom.h20 #include "llvm/MC/MCInst.h"
115 MCInst Inst;
118 MCDecodedInst(const MCInst &Inst, uint64_t Address, uint64_t Size)
133 void addInst(const MCInst &Inst, uint64_t Size);
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCAsmBackend.cpp131 bool mayNeedRelaxation(const MCInst &Inst) const override {
145 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {

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