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Searched refs:HalfVT (Results 1 - 8 of 8) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A D	ValueTypes.h	`276 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); local 277 if (HalfVT.getSizeInBits() * 2 >= EVTSize) 278 return HalfVT;`
/external/llvm/lib/Target/R600/
H A D	R600ISelLowering.cpp	891 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); local 893 SDValue one = DAG.getConstant(1, HalfVT); 894 SDValue zero = DAG.getConstant(0, HalfVT); 898 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero); 899 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one); 902 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero); 903 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one); 906 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo); 907 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo); 915 const unsigned halfBitWidth = HalfVT [all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A D	LegalizeTypes.cpp	`1096 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), local 1098 SplitInteger(Op, HalfVT, HalfVT, Lo, Hi);`
H A D	LegalizeVectorTypes.cpp	`1473 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, local 1475 SDValue HalfLo = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InLoVec); 1476 SDValue HalfHi = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InHiVec);`
H A D	TargetLowering.cpp	`855 EVT HalfVT = Op.getOperand(0).getValueType(); local 856 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();`
H A D	SelectionDAGBuilder.cpp	`129 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); local 133 PartVT, HalfVT, V); 135 RoundParts / 2, PartVT, HalfVT, V); 137 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 138 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);`
/external/llvm/lib/Target/X86/
H A D	X86ISelLowering.cpp	6862 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(), local 6866 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl), 6867 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl); 12797 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(), 12800 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo); 12801 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi); 20848 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 20850 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr, 20855 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
/external/llvm/lib/Target/AArch64/
H A D	AArch64ISelLowering.cpp	`7342 EVT HalfVT = local 7344 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, 7346 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,`

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