| /external/libhevc/decoder/arm/ |
| H A D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 116 MOVW R10,#0x3311
117 VMOV.16 D0[0],R10 @//C1
119 MOVW R10,#0xF379
120 VMOV.16 D0[1],R10 @//C2
122 MOVW R10,#0xE5F8
123 VMOV.16 D0[2],R10 @//C3
125 MOVW R10,#0x4092
126 VMOV.16 D0[3],R10 @//C4
129 MOV R10,#128
130 VDUP.8 D1,R10
[all...] |
| /external/kernel-headers/original/uapi/asm-x86/asm/ |
| H A D | ptrace-abi.h | 36 #define R10 56 macro
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.h | 27 // are still a few places that R11 and R10 are hard wired.
36 #define HEXAGON_RESERVED_REG_1 Hexagon::R10
|
| /external/libunwind/src/x86_64/ |
| H A D | unwind_i.h | 49 #define R10 10 macro
|
| H A D | init.h | 59 c->dwarf.loc[R10] = REG_INIT_LOC(c, r10, R10);
|
| H A D | Gregs.c | 115 case UNW_X86_64_R10: loc = c->dwarf.loc[R10]; break;
|
| H A D | Gos-freebsd.c | 121 c->dwarf.loc[R10] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_R10, 0);
133 c->dwarf.loc[RCX] = c->dwarf.loc[R10];
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 45 case R8: case R9: case R10: case R11: case R12:
56 case R8: case R9: case R10: case R11: case R12:
|
| H A D | Thumb1FrameLowering.cpp | 146 case ARM::R10:
208 case ARM::R10:
|
| H A D | ARMFrameLowering.cpp | 224 case ARM::R10:
384 case ARM::R10:
449 case ARM::R10:
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreRegisterInfo.cpp | 216 XCore::R8, XCore::R9, XCore::R10,
239 Reserved.set(XCore::R10);
328 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
|
| H A D | XCoreFrameLowering.cpp | 34 static const unsigned FramePtr = XCore::R10;
427 assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) &&
457 assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) &&
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| H A D | sigframe-arm-linux.c | 148 SC2(r10,R10);
327 REST(r10,R10);
|
| H A D | sigframe-amd64-linux.c | 347 SC2(r10,R10);
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.cpp | 582 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
619 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
655 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
691 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
692 return X86::R10;
|
| H A D | X86FrameLowering.cpp | 105 X86::R8, X86::R9, X86::R10, X86::R11, 0
1352 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1362 allocMBB->addLiveIn(X86::R10);
1468 // Functions with nested arguments use R10, so it needs to be saved across
1472 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1474 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1478 MF.getRegInfo().setPhysRegUsed(X86::R10);
|
| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| H A D | PPCDisassembler.cpp | 141 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
152 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 181 ENTRY(R10) \
199 ENTRY(R10) \
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86BaseInfo.h | 732 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
|
| /external/valgrind/main/VEX/auxprogs/ |
| H A D | genoffsets.c | 113 GENOFFSET(AMD64,amd64,R10);
|
| /external/libunwind/src/ptrace/ |
| H A D | _UPT_reg_offset.c | 303 UNW_R_OFF(R10, r10)
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 353 case X86::R10: return X86::R10D;
|
| /external/chromium_org/third_party/libvpx/source/libvpx/third_party/libyuv/source/ |
| H A D | x86inc.asm | 316 DECLARE_REG 4, R10, 40
393 DECLARE_REG 7, R10, 16
|
| /external/chromium_org/third_party/libvpx/source/libvpx/third_party/x86inc/ |
| H A D | x86inc.asm | 421 DECLARE_REG 4, R10, R10D, R10W, R10B, 40
501 DECLARE_REG 7, R10, R10D, R10W, R10B, 16
|
| /external/chromium_org/third_party/libyuv/source/ |
| H A D | x86inc.asm | 316 DECLARE_REG 4, R10, 40
393 DECLARE_REG 7, R10, 16
|