Searched refs:R12 (Results 1 - 25 of 36) sorted by relevance

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/external/kernel-headers/original/uapi/asm-x86/asm/
H A Dptrace-abi.h31 #define R12 24 macro
/external/libunwind/src/x86_64/
H A DGget_save_loc.c43 case UNW_X86_64_R12: loc = c->dwarf.loc[R12]; break;
H A Dunwind_i.h51 #define R12 12 macro
H A Dinit.h61 c->dwarf.loc[R12] = REG_INIT_LOC(c, r12, R12);
H A DGregs.c117 case UNW_X86_64_R12: loc = c->dwarf.loc[R12]; break;
H A DGos-freebsd.c123 c->dwarf.loc[R12] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_R12, 0);
/external/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h45 case R8: case R9: case R10: case R11: case R12:
56 case R8: case R9: case R10: case R11: case R12:
H A DThumb1RegisterInfo.cpp513 // the function, the offset will be negative. Use R12 instead since that's
518 .addReg(ARM::R12, RegState::Define)
522 // interference with R12 before then, however, we'll need to restore it
528 // If this instruction affects R12, adjust our restore point.
531 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) {
539 if (MO.getReg() == ARM::R12) {
546 // Restore the register from R12
548 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
H A DARMFrameLowering.cpp226 case ARM::R12:
326 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
332 .addReg(ARM::R12, RegState::Kill)
386 case ARM::R12:
451 case ARM::R12:
1610 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
H A DThumb1FrameLowering.cpp210 case ARM::R12:
/external/libhevc/decoder/arm/
H A Dihevcd_fmt_conv_420sp_to_rgba8888.s91 STMFD SP!,{R4-R12,LR}
145 @SUB R12,R8,R3, LSR #1 @// v offset
438 @ADD R2,R2,R12 @// adjust v pointer
448 LDMFD SP!,{R4-R12,PC}
/external/valgrind/main/coregrind/m_sigframe/
H A Dsigframe-arm-linux.c150 SC2(ip,R12);
329 REST(ip,R12);
H A Dsigframe-amd64-linux.c349 SC2(r12,R12);
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp603 Value *R11,*R12; local
605 if (decomposeBitTestICmp(RHS, RHSCC, R11, R12, R2)) {
607 A = R11; D = R12;
608 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) {
609 A = R12; D = R11;
615 if (!match(R1, m_And(m_Value(R11), m_Value(R12)))) {
619 R12
[all...]
/external/llvm/lib/Target/X86/
H A DX86RegisterInfo.cpp586 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
623 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
659 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
695 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
696 return X86::R12;
/external/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp553 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
554 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
855 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
1407 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1412 .addReg(PPC::R12,
1443 PPC::R12),
1446 MoveReg = PPC::R12;
H A DPPCAsmPrinter.cpp942 .addReg(PPC::R12)
946 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::MTCTR).addReg(PPC::R12));
996 .addReg(PPC::R12)
1001 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::MTCTR).addReg(PPC::R12));
/external/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp142 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
153 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
/external/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h183 ENTRY(R12) \
201 ENTRY(R12) \
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h733 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
/external/valgrind/main/VEX/auxprogs/
H A Dgenoffsets.c115 GENOFFSET(AMD64,amd64,R12);
/external/libunwind/src/ptrace/
H A D_UPT_reg_offset.c305 UNW_R_OFF(R12, r12)
/external/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h355 case X86::R12: return X86::R12D;
/external/chromium_org/third_party/libvpx/source/libvpx/third_party/libyuv/source/
H A Dx86inc.asm323 DECLARE_REG 11, R12, 96
397 DECLARE_REG 11, R12, 48
/external/chromium_org/third_party/libvpx/source/libvpx/third_party/x86inc/
H A Dx86inc.asm428 DECLARE_REG 11, R12, R12D, R12W, R12B, 96
505 DECLARE_REG 11, R12, R12D, R12W, R12B, 48

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