Searched refs:getOpcode (Results 1 - 25 of 588) sorted by relevance

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/external/smali/dexlib2/src/main/java/org/jf/dexlib2/iface/instruction/
H A DInstruction.java49 Opcode getOpcode(); method in interface:Instruction
/external/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h35 return Info->get(Inst.getOpcode()).isBranch();
39 return Info->get(Inst.getOpcode()).isConditionalBranch();
43 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
47 return Info->get(Inst.getOpcode()).isIndirectBranch();
51 return Info->get(Inst.getOpcode()).isCall();
55 return Info->get(Inst.getOpcode()).isReturn();
59 return Info->get(Inst.getOpcode()).isTerminator();
/external/smali/dexlib2/src/main/java/org/jf/dexlib2/analysis/
H A DUnresolvedOdexInstruction.java52 @Override public Opcode getOpcode() { method in class:UnresolvedOdexInstruction
53 return originalInstruction.getOpcode();
/external/dexmaker/src/dx/java/com/android/dx/dex/code/
H A DFixedSizeInsn.java53 return getOpcode().getFormat().codeSize();
59 getOpcode().getFormat().writeTo(out, this);
71 return getOpcode().getFormat().listingString(this, noteIndices);
/external/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp82 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
83 Addr.getOpcode() == ISD::TargetGlobalAddress ||
84 Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
87 if (Addr.getOpcode() == ISD::ADD) {
102 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
107 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
119 if (Addr.getOpcode() == ISD::FrameIndex) return false;
120 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
121 Addr.getOpcode() == ISD::TargetGlobalAddress ||
122 Addr.getOpcode()
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H A DDelaySlotFiller.cpp121 (MI->getOpcode() == SP::RESTORErr
122 || MI->getOpcode() == SP::RESTOREri)) {
128 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD
129 || MI->getOpcode() == SP::FCMPQ)) {
180 if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL)
183 if (slot->getOpcode() == SP::RETL) {
187 if (J->getOpcode() == SP::RESTORErr
188 || J->getOpcode()
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/external/llvm/lib/MC/
H A DMCInstrAnalysis.cpp16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
H A DMCInst.cpp43 OS << "<MCInst " << getOpcode();
54 OS << "<MCInst #" << getOpcode();
58 OS << ' ' << Printer->getOpcodeName(getOpcode());
/external/dexmaker/src/dx/java/com/android/dx/ssa/
H A DNormalSsaInsn.java128 public Rop getOpcode() { method in class:NormalSsaInsn
129 return insn.getOpcode();
143 if (insn.getOpcode().getOpcode() == RegOps.MARK_LOCAL) {
180 return insn.getOpcode().getOpcode() == RegOps.MOVE;
186 return insn.getOpcode().getOpcode() == RegOps.MOVE_EXCEPTION;
218 Rop opcode = getOpcode();
227 switch (opcode.getOpcode()) {
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/external/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp129 if (II->getOpcode() == TargetOpcode::KILL)
179 if (MII->getOpcode() == Hexagon::CALLv3)
193 if (MII->getOpcode() == TargetOpcode::KILL ||
194 MII->getOpcode() == TargetOpcode::PHI ||
195 MII->getOpcode() == TargetOpcode::COPY)
202 if (MII->getOpcode() == Hexagon::TFR_condset_rr ||
203 MII->getOpcode() == Hexagon::TFR_condset_ii ||
204 MII->getOpcode() == Hexagon::TFR_condset_ri ||
205 MII->getOpcode() == Hexagon::TFR_condset_ir ||
206 MII->getOpcode()
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H A DHexagonRegisterInfo.cpp145 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
153 if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
162 if ( (MI.getOpcode() == Hexagon::LDriw) ||
163 (MI.getOpcode() == Hexagon::LDrid) ||
164 (MI.getOpcode() == Hexagon::LDrih) ||
165 (MI.getOpcode() == Hexagon::LDriuh) ||
166 (MI.getOpcode() == Hexagon::LDrib) ||
167 (MI.getOpcode() == Hexagon::LDriub) ||
168 (MI.getOpcode() == Hexagon::LDriw_f) ||
169 (MI.getOpcode()
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/external/llvm/lib/Target/R600/
H A DR600EmitClauseMarkers.cpp41 switch (MI->getOpcode()) {
55 if (TII->isLDSRetInstr(MI->getOpcode()))
59 TII->isCubeOp(MI->getOpcode()) ||
60 TII->isReductionOp(MI->getOpcode()))
74 if (TII->isALUInstr(MI->getOpcode()))
76 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode()))
78 switch (MI->getOpcode()) {
92 switch (MI->getOpcode()) {
121 if (!TII->isALUInstr(MI->getOpcode()) && MI->getOpcode() !
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/external/llvm/lib/Target/PowerPC/
H A DPPCBranchSelector.cpp117 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm())
119 else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) &&
122 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ ||
123 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) &&
162 if (I->getOpcode() == PPC::BCC) {
173 } else if (I->getOpcode() == PPC::BC) {
176 } else if (I->getOpcode()
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/external/dexmaker/src/dx/java/com/android/dx/rop/code/
H A DPlainInsn.java92 return new PlainInsn(getOpcode(), getPosition(),
115 Rop newRop = Rops.ropFor(getOpcode().getOpcode(), getResult(),
130 int opcode = getOpcode().getOpcode();
152 return new PlainInsn(getOpcode(), getPosition(),
H A DThrowingCstInsn.java84 return new ThrowingCstInsn(getOpcode(), getPosition(),
92 return new ThrowingCstInsn(getOpcode(), getPosition(),
103 return new ThrowingCstInsn(getOpcode(), getPosition(),
H A DThrowingInsn.java99 return new ThrowingInsn(getOpcode(), getPosition(),
106 return new ThrowingInsn(getOpcode(), getPosition(),
116 return new ThrowingInsn(getOpcode(), getPosition(),
/external/llvm/unittests/Transforms/Utils/
H A DIntegerDivision.cpp42 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SDiv);
47 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr);
50 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::Sub);
72 EXPECT_TRUE(BB->front().getOpcode() == Instruction::UDiv);
77 EXPECT_TRUE(BB->front().getOpcode() == Instruction::ICmp);
80 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::PHI);
102 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem);
107 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr);
110 EXPECT_TRUE(Remainder && Remainder->getOpcode() == Instruction::Sub);
132 EXPECT_TRUE(BB->front().getOpcode()
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/external/dexmaker/src/dx/java/com/android/dx/io/instructions/
H A DZeroRegisterDecodedInstruction.java41 getFormat(), getOpcode(), newIndex, getIndexType(),
/external/smali/dexlib2/src/main/java/org/jf/dexlib2/writer/
H A DInstructionWriter.java82 writer.write(instruction.getOpcode().value);
91 writer.write(instruction.getOpcode().value);
100 writer.write(instruction.getOpcode().value);
109 writer.write(instruction.getOpcode().value);
118 writer.write(instruction.getOpcode().value);
127 writer.write(instruction.getOpcode().value);
137 writer.write(instruction.getOpcode().value);
147 writer.write(instruction.getOpcode().value);
157 writer.write(instruction.getOpcode().value);
167 writer.write(instruction.getOpcode()
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/external/llvm/include/llvm/IR/
H A DInstruction.h85 /// getOpcode() returns a member of one of the enums like Instruction::Add.
86 unsigned getOpcode() const { return getValueID() - InstructionVal; } function in class:llvm::Instruction
88 const char *getOpcodeName() const { return getOpcodeName(getOpcode()); }
89 bool isTerminator() const { return isTerminator(getOpcode()); }
90 bool isBinaryOp() const { return isBinaryOp(getOpcode()); }
91 bool isShift() { return isShift(getOpcode()); }
92 bool isCast() const { return isCast(getOpcode()); }
112 return getOpcode() == Shl || getOpcode() == LShr;
117 return getOpcode()
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H A DOperator.h49 /// getOpcode - Return the opcode for this Instruction or ConstantExpr.
51 unsigned getOpcode() const { function in class:llvm::Operator
53 return I->getOpcode();
54 return cast<ConstantExpr>(this)->getOpcode();
57 /// getOpcode - If V is an Instruction or ConstantExpr, return its
60 static unsigned getOpcode(const Value *V) { function in class:llvm::Operator
62 return I->getOpcode();
64 return CE->getOpcode();
112 return I->getOpcode() == Instruction::Add ||
113 I->getOpcode()
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/external/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h177 inline unsigned getOpcode() const;
397 /// getOpcode - Return the SelectionDAG opcode value for this node. For
401 unsigned getOpcode() const { return (unsigned short)NodeType; } function in class:llvm::SDNode
880 inline unsigned SDValue::getOpcode() const { function in class:llvm::SDValue
881 return Node->getOpcode();
991 return isBinOpWithFlags(N->getOpcode());
1036 return N->getOpcode() == ISD::ADDRSPACECAST;
1123 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
1130 return N->getOpcode() == ISD::LOAD ||
1131 N->getOpcode()
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp92 switch (MI.getOpcode()) {
136 if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS)
183 if (LastInst->getOpcode() == NVPTX::GOTO) {
186 } else if (LastInst->getOpcode() == NVPTX::CBranch) {
204 if (SecondLastInst->getOpcode() == NVPTX::CBranch &&
205 LastInst->getOpcode() == NVPTX::GOTO) {
214 if (SecondLastInst->getOpcode() == NVPTX::GOTO &&
215 LastInst->getOpcode() == NVPTX::GOTO) {
232 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() !
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/external/llvm/lib/Target/AArch64/
H A DAArch64BranchRelaxation.cpp292 switch (MI->getOpcode()) {
345 assert(MI->getOpcode() == AArch64::Bcc && "Unexpected opcode!");
375 BMI->getOpcode() == AArch64::B) {
385 getBranchDisplacementBits(MI->getOpcode()))) {
389 unsigned OpNum = (MI->getOpcode() == AArch64::TBZW ||
390 MI->getOpcode() == AArch64::TBNZW ||
391 MI->getOpcode() == AArch64::TBZX ||
392 MI->getOpcode() == AArch64::TBNZX)
396 MI->setDesc(TII->get(getOppositeConditionOpcode(MI->getOpcode())));
397 if (MI->getOpcode()
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/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64ExternalSymbolizer.cpp91 } else if (MI.getOpcode() == AArch64::ADRP) {
104 } else if (MI.getOpcode() == AArch64::ADDXri ||
105 MI.getOpcode() == AArch64::LDRXui ||
106 MI.getOpcode() == AArch64::LDRXl ||
107 MI.getOpcode() == AArch64::ADR) {
108 if (MI.getOpcode() == AArch64::ADDXri)
110 else if (MI.getOpcode() == AArch64::LDRXui)
112 if (MI.getOpcode() == AArch64::LDRXl) {
116 } else if (MI.getOpcode() == AArch64::ADR) {
125 MI.getOpcode()
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