/external/clang/test/SemaTemplate/ |
H A D | value-dependent-null-pointer-constant.cpp | 5 const char *f0(bool Cond) { argument 6 return Cond? "honk" : N; 9 const char *f1(bool Cond) { argument 10 return Cond? N : "honk";
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H A D | instantiate-expr-2.cpp | 77 struct Cond { 81 enum { resultT = Cond<true>::is, 82 resultF = Cond<false>::is }; 92 struct Cond { struct in namespace:N6 97 typedef Cond<true, int, char>::True True; 98 typedef Cond<true, int, char>::False False; 112 struct Cond { struct in namespace:N7 117 //Cond<true, int*, double> C; // Errors 119 //typedef Cond<true, int*, double>::Type Type; // Errors 120 typedef Cond<tru [all...] |
H A D | constructor-template.cpp | 60 X2 test(bool Cond, X2 x2) { argument 61 if (Cond) 80 X4 test_X4(bool Cond, X4 x4) { argument
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/external/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 73 SmallVectorImpl<MachineOperand> &Cond) const { 80 Cond.push_back(MachineOperand::CreateImm(Opc)); 83 Cond.push_back(Inst->getOperand(i)); 89 SmallVectorImpl<MachineOperand> &Cond, 92 BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); 99 const SmallVectorImpl<MachineOperand>& Cond) 101 unsigned Opc = Cond[0].getImm(); 105 for (unsigned i = 1; i < Cond.size(); ++i) { 106 if (Cond[i].isReg()) 107 MIB.addReg(Cond[ 86 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 117 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument 184 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify, SmallVectorImpl<MachineInstr*> &BranchInstrs) const argument [all...] |
H A D | MipsInstrInfo.h | 56 SmallVectorImpl<MachineOperand> &Cond, 63 const SmallVectorImpl<MachineOperand> &Cond, 67 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 71 SmallVectorImpl<MachineOperand> &Cond, 136 SmallVectorImpl<MachineOperand> &Cond) const; 139 const SmallVectorImpl<MachineOperand>& Cond) const;
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/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
H A D | ConstraintManager.h | 68 DefinedSVal Cond, 75 ProgramStatePair assumeDual(ProgramStateRef State, DefinedSVal Cond) { argument 76 ProgramStateRef StTrue = assume(State, Cond, true); 78 // If StTrue is infeasible, asserting the falseness of Cond is unnecessary 86 assert(assume(State, Cond, false) && "System is over constrained."); 91 ProgramStateRef StFalse = assume(State, Cond, false);
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/external/clang/test/SemaCXX/ |
H A D | vector.cpp | 40 void conditional(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, argument 43 __typeof__(Cond? c16 : c16) *c16p1 = &c16; 44 __typeof__(Cond? ll16 : ll16) *ll16p1 = &ll16; 45 __typeof__(Cond? c16e : c16e) *c16ep1 = &c16e; 46 __typeof__(Cond? ll16e : ll16e) *ll16ep1 = &ll16e; 49 __typeof__(Cond? c16 : c16e) *c16ep2 = &c16e; 50 __typeof__(Cond? c16e : c16) *c16ep3 = &c16e; 51 __typeof__(Cond? ll16 : ll16e) *ll16ep2 = &ll16e; 52 __typeof__(Cond? ll16e : ll16) *ll16ep3 = &ll16e; 55 (void)(Cond 108 test_implicit_conversions(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, longlong16_e ll16e, convertible_to<char16> to_c16, convertible_to<longlong16> to_ll16, convertible_to<char16_e> to_c16e, convertible_to<longlong16_e> to_ll16e, convertible_to<char16&> rto_c16, convertible_to<char16_e&> rto_c16e) argument [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
H A D | radeon_emulate_loops.h | 12 struct rc_instruction * Cond; member in struct:loop_info
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H A D | radeon_emulate_loops.c | 199 if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[0].File, 200 loop->Cond->U.I.SrcReg[0].Index)){ 201 limit = &loop->Cond->U.I.SrcReg[0]; 202 counter = &loop->Cond->U.I.SrcReg[1]; 204 else if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[1].File, 205 loop->Cond->U.I.SrcReg[1].Index)){ 206 limit = &loop->Cond->U.I.SrcReg[1]; 207 counter = &loop->Cond->U.I.SrcReg[0]; 285 switch(loop->Cond->U.I.Opcode){ 309 rc_remove_instruction(loop->Cond); [all...] |
/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_emulate_loops.h | 12 struct rc_instruction * Cond; member in struct:loop_info
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H A D | radeon_emulate_loops.c | 199 if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[0].File, 200 loop->Cond->U.I.SrcReg[0].Index)){ 201 limit = &loop->Cond->U.I.SrcReg[0]; 202 counter = &loop->Cond->U.I.SrcReg[1]; 204 else if(rc_src_reg_is_immediate(c, loop->Cond->U.I.SrcReg[1].File, 205 loop->Cond->U.I.SrcReg[1].Index)){ 206 limit = &loop->Cond->U.I.SrcReg[1]; 207 counter = &loop->Cond->U.I.SrcReg[0]; 285 switch(loop->Cond->U.I.Opcode){ 309 rc_remove_instruction(loop->Cond); [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.h | 76 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 80 SmallVectorImpl<MachineOperand> &Cond, 86 const SmallVectorImpl<MachineOperand> &Cond,
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H A D | MSP430InstrInfo.cpp | 130 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 131 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); 133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); 157 Cond[0].setImm(CC); 175 SmallVectorImpl<MachineOperand> &Cond, 210 Cond.clear(); 234 if (Cond.empty()) { 237 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 243 assert(Cond.size() == 1); 251 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[ 172 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 263 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument [all...] |
H A D | MSP430BranchSelector.cpp | 151 SmallVector<MachineOperand, 1> Cond; local 152 Cond.push_back(I->getOperand(1)); 155 TII->ReverseBranchCondition(Cond); 157 .addImm(4).addOperand(Cond[0]);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.h | 55 SmallVectorImpl<MachineOperand> &Cond, 60 const SmallVectorImpl<MachineOperand> &Cond, 83 SmallVectorImpl<MachineOperand> &Cond) const override;
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H A D | XCoreInstrInfo.cpp | 196 SmallVectorImpl<MachineOperand> &Cond, 229 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 230 Cond.push_back(LastInst->getOperand(0)); 251 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 252 Cond.push_back(SecondLastInst->getOperand(0)); 284 const SmallVectorImpl<MachineOperand> &Cond, 288 assert((Cond.size() == 2 || Cond.size() == 0) && 292 if (Cond.empty()) { 297 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[ 194 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 282 InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument [all...] |
/external/clang/lib/StaticAnalyzer/Core/ |
H A D | SimpleConstraintManager.cpp | 69 DefinedSVal Cond, 72 if (Optional<Loc> LV = Cond.getAs<Loc>()) { 81 Cond = SVB.evalCast(*LV, SVB.getContext().BoolTy, T).castAs<DefinedSVal>(); 84 return assume(state, Cond.castAs<NonLoc>(), Assumption); 115 NonLoc Cond, 120 if (!canReasonAbout(Cond)) { 122 SymbolRef sym = Cond.getAsSymExpr(); 126 switch (Cond.getSubKind()) { 131 nonloc::SymbolVal SV = Cond.castAs<nonloc::SymbolVal>(); 182 bool b = Cond 68 assume(ProgramStateRef state, DefinedSVal Cond, bool Assumption) argument 114 assumeAux(ProgramStateRef state, NonLoc Cond, bool Assumption) argument [all...] |
H A D | SimpleConstraintManager.h | 36 ProgramStateRef assume(ProgramStateRef state, DefinedSVal Cond, 39 ProgramStateRef assume(ProgramStateRef state, NonLoc Cond, bool Assumption); 88 NonLoc Cond,
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 172 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const { 189 Cond.push_back(LastInst->getOperand(0)); 207 Cond.push_back(SecondLastInst->getOperand(0)); 253 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const { 256 assert((Cond.size() == 1 || Cond.size() == 0) && 261 if (Cond.empty()) // Unconditional branch 264 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()) 270 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB); 170 AnalyzeBranch( MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 251 InsertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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H A D | NVPTXInstrInfo.h | 65 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override; 69 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override;
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.h | 68 SmallVectorImpl<MachineOperand> &Cond, 75 const SmallVectorImpl<MachineOperand> &Cond,
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600InstrInfo.cpp | 180 SmallVectorImpl<MachineOperand> &Cond, 216 Cond.push_back(predSet->getOperand(1)); 217 Cond.push_back(predSet->getOperand(2)); 218 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); 240 Cond.push_back(predSet->getOperand(1)); 241 Cond.push_back(predSet->getOperand(2)); 242 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); 264 const SmallVectorImpl<MachineOperand> &Cond, 270 if (Cond.empty()) { 277 PredSet->getOperand(2).setImm(Cond[ 177 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 261 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument [all...] |
H A D | R600InstrInfo.h | 66 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 69 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const; 71 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600InstrInfo.cpp | 180 SmallVectorImpl<MachineOperand> &Cond, 216 Cond.push_back(predSet->getOperand(1)); 217 Cond.push_back(predSet->getOperand(2)); 218 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); 240 Cond.push_back(predSet->getOperand(1)); 241 Cond.push_back(predSet->getOperand(2)); 242 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); 264 const SmallVectorImpl<MachineOperand> &Cond, 270 if (Cond.empty()) { 277 PredSet->getOperand(2).setImm(Cond[ 177 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 261 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 1207 ISD::CondCode Cond, bool foldBooleans, 1212 switch (Cond) { 1227 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond); 1244 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1246 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1249 Cond = ISD::SETNE; 1253 Cond = ISD::SETEQ; 1257 Zero, Cond); 1274 if ((Cond 1206 SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const argument [all...] |