| /external/chromium_org/v8/test/cctest/ |
| H A D | test-disasm-mips.cc | 135 COMPARE(divu(a0, a1),
136 "0085001b divu a0, a1");
137 COMPARE(divu(t2, t3),
138 "014b001b divu t2, t3");
139 COMPARE(divu(v0, v1),
140 "0043001b divu v0, v1");
190 COMPARE(divu(a0, a1, a2),
191 "00a6209b divu a0, a1, a2");
194 COMPARE(divu(t1, t2, t3),
195 "014b489b divu t
[all...] |
| H A D | test-disasm-mips64.cc | 165 COMPARE(divu(a0, a1),
166 "0085001b divu a0, a1");
167 COMPARE(divu(a6, a7),
168 "014b001b divu a6, a7");
169 COMPARE(divu(v0, v1),
170 "0043001b divu v0, v1");
259 COMPARE(divu(a0, a1, a2),
260 "00a6209b divu a0, a1, a2");
267 COMPARE(divu(a5, a6, a7),
268 "014b489b divu a
[all...] |
| /external/llvm/test/MC/Mips/ |
| H A D | micromips-alu-instructions.s | 40 # CHECK-EL: divu $zero, $9, $7 # encoding: [0xe9,0x00,0x3c,0xbb]
74 # CHECK-EB: divu $zero, $9, $7 # encoding: [0x00,0xe9,0xbb,0x3c]
106 divu $0, $9, $7
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| H A D | invalid-mips1.s | 24 # divu has been re-encoded. See valid.s
|
| H A D | invalid-mips2.s | 26 # divu has been re-encoded. See valid.s
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| H A D | invalid-mips1.s | 27 # divu has been re-encoded. See valid.s
|
| H A D | invalid-mips2.s | 29 # divu has been re-encoded. See valid.s
|
| H A D | invalid-mips3.s | 33 # divu has been re-encoded. See valid.s
|
| H A D | invalid-mips64.s | 54 # divu has been re-encoded. See valid.s
|
| /external/chromium_org/v8/src/mips64/ |
| H A D | disasm-mips64.cc | 831 Format(instr, "divu 'rs, 'rt");
834 Format(instr, "divu 'rd, 'rs, 'rt");
|
| H A D | assembler-mips64.h | 746 void divu(Register rs, Register rt);
750 void divu(Register rd, Register rs, Register rt);
|
| H A D | assembler-mips64.cc | 1549 void Assembler::divu(Register rs, Register rt) { function in class:v8::Assembler
1554 void Assembler::divu(Register rd, Register rs, Register rt) { function in class:v8::Assembler
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | valid.s | 39 divu $zero,$25,$15
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | valid.s | 41 divu $zero,$25,$15
|
| /external/llvm/test/MC/Mips/mips32/ |
| H A D | valid.s | 47 divu $zero,$25,$15
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 50 divu $zero,$25,$15
|
| /external/chromium_org/v8/src/mips/ |
| H A D | assembler-mips.h | 755 void divu(Register rs, Register rt);
757 void divu(Register rd, Register rs, Register rt);
|
| H A D | assembler-mips.cc | 1545 void Assembler::divu(Register rs, Register rt) { function in class:v8::Assembler
1550 void Assembler::divu(Register rd, Register rs, Register rt) { function in class:v8::Assembler
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 58 divu $zero,$25,$15
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | valid.s | 60 divu $zero,$25,$15
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 60 divu $zero,$25,$15
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 65 divu $zero,$25,$15
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 66 divu $zero,$25,$15
|
| /external/openssl/crypto/bn/asm/ |
| H A D | bn-mips.S | 660 divu $0,$4,$3
693 divu $0,$4,$3
|
| /external/qemu/tcg/ |
| H A D | optimize.c | 923 CASE_OP_32_64(divu):
|